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AD420ARZ-32 Fiches technique(PDF) 9 Page - Analog Devices |
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AD420ARZ-32 Fiches technique(HTML) 9 Page - Analog Devices |
9 / 16 page AD420 Rev. H | Page 9 of 16 THEORY OF OPERATION The AD420 uses a sigma-delta (Σ-Δ) architecture to carry out the digital-to-analog conversion. This architecture is particularly well suited for the relatively low bandwidth requirements of the industrial control environment because of its inherent monotonicity at high resolution. In the AD420 a second order modulator is used to keep com- plexity and die size to a minimum. The single bit stream from the modulator controls a switched current source that is then filtered by two, continuous time resistor-capacitor sections. The capacitors are the only external components that have to be added for standard current-out operation. The filtered current is amplified and mirrored to the supply rail so that the application simply sees a 4 mA–20 mA, 0 mA–20 mA, or 0 mA–24 mA current source output with respect to ground. The AD420 is manufactured on a BiCMOS process that is well suited to implementing low voltage digital logic with high performance and high voltage analog circuitry. The AD420 can also provide a voltage output instead of a current loop output if desired. The addition of a single external amplifier allows the user to obtain 0 V–5 V, 0 V–10 V, ±5 V, or ±10 V. The AD420 has a loop fault detection circuit that warns if the voltage at IOUT attempts to rise above the compliance range, due to an open-loop circuit or insufficient power supply voltage. The FAULT DETECT is an active low open drain signal so that one can connect several AD420s together to one pull-up resistor for global error detection. The pull-up resistor can be tied to the VLL pin, or an external +5 V logic supply. The IOUT current is controlled by a PMOS transistor and an internal amplifier as shown in the functional block diagram. The internal circuitry that develops the fault output avoids using a comparator with window limits since this would require an actual output error before the FAULT DETECT output becomes active. Instead, the signal is generated when the internal amplifier in the output stage of the AD420 has less than approximately one volt remaining of drive capability (when the gate of the output PMOS transistor nearly reaches ground). Thus the FAULT DETECT output activates slightly before the compliance limit is reached. Since the comparison is made within the feedback loop of the output amplifier, the output accuracy is maintained by its open-loop gain, and no output error occurs before the fault detect output becomes active. The 3-wire digital interface, comprising DATA IN, CLOCK, and LATCH, interfaces to all commonly used serial micropro- cessors without the addition of any external glue logic. Data is loaded into an input register under control of CLOCK and is loaded to the DAC when LATCH is strobed. If a user wants to minimize the number of galvanic isolators in an intrinsically safe application, the AD420 can be configured to run in asynchronous mode. This mode is selected by connecting the LATCH pin to VCC through a current limiting resistor. The data must then be combined with a start and stop bit to frame the information and trigger the internal LATCH signal. FAULT DETECT IOUT BOOST 40Ω 1.25kΩ 4kΩ VOUT OFFSET TRIM CAP 1 CAP 2 GND VLL VCC REF OUT REF IN DATA OUT CLEAR LATCH CLOCK DATA IN RANGE SELECT 1 RANGE SELECT 2 AD420 REFERENCE DATA I/P REGISTER SWITCHED CURRENT SOURCES AND FILTERING CLOCK 16-BIT DAC 2 19 23 18 17 3 21 11 20 16 14 15 10 6 7 8 9 5 4 Figure 5. Functional Block Diagram |
Numéro de pièce similaire - AD420ARZ-32 |
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Description similaire - AD420ARZ-32 |
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