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AD420AR-32 Fiches technique(PDF) 7 Page - Analog Devices |
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AD420AR-32 Fiches technique(HTML) 7 Page - Analog Devices |
7 / 16 page AD420 Rev. H | Page 7 of 16 TIMING REQUIREMENTS CLOCK DATA IN CLOCK DATA IN (INTERNALLY GENERATED LATCH) EXPANDED TIME VIEW BELOW CLOCK COUNTER STARTS HERE CONFIRM START BIT SAMPLE BIT 15 START BIT DATA BIT 15 BIT 14 EXPANDED TIME VIEW BELOW CLOCK DATA IN 01 012 8 16 24 00 1 tADW tADS tADH tACH tACL tACK TA = −40°C to +85°C, VCC = +12 V to +32 V. THREE-WIRE INTERFACE CLOCK DATA IN LATCH DATA OUT CLOCK DATA IN LATCH DATA OUT WORD “N” WORD “N + 1” WORD “N – 1” WORD “N” 101 1 0 0 1 1 1 00 1 1 111 0 0 0 0 11 01 tCK tCL tCH tDW tLD tLL tLH tSD tDS tDH Figure 4. Timing Diagram for Asynchronous Interface Figure 3. Timing Diagram for 3-Wire Interface Table 6. Timing Specifications for Asynchronous Interface Parameter Label Limit Units Asynchronous Clock Period tACK 400 ns min Asynchronous Clock Low Time tACL 50 ns min Asynchronous Clock High Time tACH 150 ns min Data Stable Width (Critical Clock Edge) tADW 300 ns min Data Setup Time (Critical Clock Edge) tADS 60 ns min Data Hold Time (Critical Clock Edge) tADH 20 ns min Clear Pulse Width tCLR 50 ns min Table 5. Timing Specification for 3-Wire Interface Parameter Label Limit Units Data Clock Period tCK 300 ns min Data Clock Low Time tCL 80 ns min Data Clock High Time tCH 80 ns min Data Stable Width tDW 125 ns min Data Setup Time tDS 40 ns min Data Hold Time tDH 5 ns min Latch Delay Time tLD 80 ns min Latch Low Time tLL 80 ns min Latch High Time tLH 80 ns min Serial Output Delay Time tSD 225 ns max Clear Pulse Width tCLR 50 ns min ASYNCHRONOUS INTERFACE Note that in the timing diagram for asynchronous mode oper- ation each data word is framed by a START (0) bit and a STOP (1) bit. The data timing is with respect to the rising edge of the CLOCK at the center of each bit cell. Bit cells are 16 clocks long, and the first cell (the START bit) begins at the first clock following the leading (falling) edge of the START bit. Thus, the MSB (D15) is sampled 24 clock cycles after the beginning of the START bit, D14 is sampled at clock number 40, and so on. During any dead time before writing the next word the DATA IN pin must remain at Logic 1. THREE-WIRE INTERFACE FAST EDGES ON DIGITAL INPUT With a fast rising edge (<10 ns) on one of the serial inputs (CLOCK, DATA IN, LATCH) while another input is logic high, the part may be triggered into a test mode and the contents of the data register may become corrupted, which may result in the output being loaded with an incorrect value. If fast edges are expected on the digital input lines, it is recommended that the latch line remain at Logic 0 during serial loading of the DAC. Similarly, the clock line should remain low during updates of the DAC via the latch pin. Alternatively, the addition of small value capacitors on the digital lines will slow down the edge. The DAC output updates when the STOP bit is received. In the case of a framing error (the STOP bit sampled as a 0) the AD420 will output a pulse at the DATA OUT pin one clock period wide during the clock period subsequent to sampling the STOP bit. The DAC output will not update if a framing error is detected. |
Numéro de pièce similaire - AD420AR-32 |
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Description similaire - AD420AR-32 |
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