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CAT25C04U14I-TE13 Fiches technique(PDF) 4 Page - Catalyst Semiconductor |
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CAT25C04U14I-TE13 Fiches technique(HTML) 4 Page - Catalyst Semiconductor |
4 / 10 page 4 CAT25C01/02/04/08/16 Doc. No. 25067-00 5/00 Advanced Information FUNCTIONAL DESCRIPTION The CAT25C01/02/04/08/16 supports the SPI bus data transmission protocol. The synchronous Serial Periph- eral Interface (SPI) helps the CAT25C01/02/04/08/16 to interface directly with many of today’s popular microcontrollers. The CAT25C01/02/04/08/16 contains an 8-bit instruction register. (The instruction set and the operation codes are detailed in the instruction set table) After the device is selected with CS going low, the first byte will be received. The part is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The first byte contains one of the six op-codes that define the operation to be performed. PIN DESCRIPTION SI: Serial Input SI is the serial data input pin. This pin is used to input all opcodes, byte addresses, and data to be written to the 25C01/02/04/08/16. Input data is latched on the rising edge of the serial clock for SPI modes (0, 0 & 1, 1). SO: Serial Output SO is the serial data output pin. This pin is used to transfer data out of the 25C01/02/04/08/16. During a read cycle, data is shifted out on the falling edge of the serial clock for SPI modes (0,0 & 1,1). SCK: Serial Clock SCK is the serial clock pin. This pin is used to synchro- nize the communication between the microcontroller and the 25C01/02/04/08/16. Opcodes, byte addresses, or data present on the SI pin are latched on the rising edge of the SCK. Data on the SO pin is updated on the falling edge of the SCK for SPI modes (0,0 & 1,1) . CS CS CS CS CS: Chip Select CS is the Chip select pin. CS low enables the CAT25C01/ 02/04/08/16 and CS high disables the CAT25C01/02/ 04/08/16. CS high takes the SO output pin to high impedance and forces the devices into a Standby Mode (unless an internal write operation is underway) The CAT25C01/02/04/08/16 draws ZERO current in the Standby mode. A high to low transition on CS is required prior to any sequence being initiated. A low to high transition on CS after a valid write sequence is what initiates an internal write cycle. WP WP WP WP WP: Write Protect WP is the Write Protect pin. The Write Protect pin will allow normal read/write operations when held high. When WP is tied low and the WPEN bit in the status register is set to “1”, all write operations to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit is set to 0. Figure 10 illustrates the WP timing sequence during a write operation. Instruction Opcode Operation WREN 0000 0110 Enable Write Operations WRDI 0000 0100 Disable Write Operations RDSR 0000 0101 Read Status Register WRSR 0000 0001 Write Status Register READ 0000 X011(1) Read Data from Memory WRITE 0000 X010(1) Write Data to Memory INSTRUCTION SET Note: (1) X=0 for 25C01, 25C02, 25C08, 25C16. X=A8 for 25C04 (2) This parameter is tested initially and after a design or process change that affects the parameter. (3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. Power-Up Timing(2)(3) Symbol Parameter Max. Units tPUR Power-up to Read Operation 1 ms tPUW Power-up to Write Operation 1 ms |
Numéro de pièce similaire - CAT25C04U14I-TE13 |
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Description similaire - CAT25C04U14I-TE13 |
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