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CAT28C17APA-20T Fiches technique(PDF) 6 Page - Catalyst Semiconductor |
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CAT28C17APA-20T Fiches technique(HTML) 6 Page - Catalyst Semiconductor |
6 / 8 page CAT28C17A 6 Doc. No. 25034-00 2/98 ADDRESS CE OE WE tRC DATA OUT DATA VALID DATA VALID tCE tOE tOH tAA tOHZ tHZ VIH HIGH-Z tLZ tOLZ DEVICE OPERATION Read Data stored in the CAT28C17A is transferred to the data bus when WE is held high, and both OE and CE are held low. The data bus is set to a high impedance state when either CE or OE goes high. This 2-line control architec- ture can be used to eliminate bus contention in a system environment. 28C17A F05 Figure 4. Byte Write Cycle [WE Controlled] ADDRESS CE OE WE tAS DATA IN DATA VALID tCS tAH tCH tWC tOEH tDL tDH tDS tOES tWP RDY/BUSY tDB DATA OUT HIGH-Z 5091 FHD F06 Ready/BUSY (RDY/BUSY) The RDY/BUSY pin is an open drain output which indicates device status during programming. It is pulled low during the write cycle and released at the end of programming. Several devices may be OR-tied to the same RDY/BUSY line. Figure 3. Read Cycle |
Numéro de pièce similaire - CAT28C17APA-20T |
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Description similaire - CAT28C17APA-20T |
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