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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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OPA655 Fiches technique(PDF) 13 Page - Burr-Brown (TI) |
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OPA655 Fiches technique(HTML) 13 Page - Burr-Brown (TI) |
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13 / 14 page  13 ® OPA655 THERMAL CONSIDERATIONS The OPA655 will not require heatsinking under most oper- ating conditions. Maximum desired junction temperature will limit the maximum allowed internal power dissipation as described below. In no case should the maximum junction temperature be allowed to exceed +175 °C. Operating junction temperature (TJ) is given by TA + PD • θJA. The total internal power dissipation (PD) is a combination of the quiescent power plus the power dissi- pated in the output stage to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL will depend on the required output signal and load but would, for a grounded resistive load, be at a maximum when the output is a fixed DC voltage equal to 1/2 of either supply voltage (assuming equal bipolar supplies). Under this condition P DL = VS 2/(4 • R L) where RL includes feedback network loading. Note that it is the power dissipated in the output stage and not in the load that determines internal power dissipation. As an example, compute the maximum TJ for the OPA655U at G = +2, R L = 100Ω, RF = 100Ω, ±VS = ±5V, and at the specified maximum T A = 85°C. PD = 10V • 31mA + (52)/[4 • (100 || 200)] = 404mW. Maximum T J = 85 °C + 0.404W • 125°C/W = 136°C. LAYOUT AND INTERCONNECT CONSIDERATIONS Achieving optimum performance with a high frequency amplifier like the OPA655 requires careful attention to layout parasitics and selection of external components. Sug- gestions include: • Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability; on the non- inverting input it can react with the source impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes. Other- wise, ground and power planes should be unbroken else- where on the board. • Minimize the distance (< 0.25") from the four power pins to high frequency 0.1 µF decoupling capacitors. At the pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. The OPA655 may be operated with only pins 4 and 7 connected as supply pins allowing a direct replacement into existing 8 pin op amp pinouts. Connecting the output stage power pins separately, and decoupling them, will give the best distor- tion and settling performance. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. Larger (2.2 µF to 6.8µF) decoupling capacitors, effective at lower frequencies, should also be used. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board. DIFFERENTIAL GAIN AND DIFFERENTIAL PHASE The OPA655 provides one of the lowest dG/dP errors of any op amp. This specification is the change in the small signal gain and phase for a composite video color carrier frequency when the output voltage is slowly ramped over the lumi- nance range. The specifications show less than 0.01%/0.01 ° for positive NTSC into a single video load. This level of performance challenges the accuracy of commercially avail- able video test equipment. Measurements were taken using an HP9480 IC parametric test system. OUTPUT DRIVE CAPABILITY The guaranteed output current of ±28mA will drive a 100Ω load over the full guaranteed output voltage range of ±2.8V. These minimum performance levels are only applicable at cold temperatures, with higher output voltage and current available in most applications. Many demanding high speed applications, such as driving ADC’s, require amplifiers with low, broadband, output impedance. As shown in Figure 13, the OPA655 maintains a very low closed loop output imped- ance over frequency. Closed loop output impedance in- creases with frequency as the loop gain rolls off. FIGURE 12. 5MHz Harmonic Distortion vs Load Resistance. –50 –60 –70 –80 –90 –100 10 100 1000 Load Resistance ( Ω) 2f O 3f O V O = 2Vp-p, G = +5, fO = 5MHz FIGURE 13. Small-Signal Output Impedance vs Frequency. 10 1 0.01 0.1 0.001 10k 100k 1M 10M 100M Frequency (Hz) G = +1 |
Numéro de pièce similaire - OPA655 |
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Description similaire - OPA655 |
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