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AD8842AN Fiches technique(PDF) 10 Page - Analog Devices |
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AD8842AN Fiches technique(HTML) 10 Page - Analog Devices |
10 / 13 page REV. –10– AD8842 ADJUSTING AC OR DC SIGNAL LEVELS The four-quadrant multiplication operation of the AD8842 is shown in Figure 27. For dc operation the equation describing the relationship between VIN, digital inputs and VOUT is: VOUT(D) = (D/128-1) × V IN (1) where D is a decimal number between 0 and 255 The actual output voltages generated with a fixed 3 V dc input applied to VIN are summarized in this table. Table III. Decimal Comments Input (D) VOUT(D) (VIN = 3 V) 0 –3.00 V Inverted FS 1 –2.98 127 –0.02 128 0.00 Zero Output 129 0.02 254 2.95 255 2.98 Full Scale (FS) Notice that the output polarity is the same as the input polarity when the DAC register is loaded with 255 (in binary = all ones). Also note that the output does not exactly equal the input volt- age. This is a result of the R-2R ladder DAC architecture cho- sen. When the DAC register is loaded with 0, the output polarity is inverted and exactly equals the magnitude of the in- put voltage VIN. The actual voltage measured when setting up a DAC in this example will vary within the ±1 LSB linearity error specification of the AD8842. The calculated voltage error would be ±0.023 V (= ±3 V/128). If VIN is an ac signal such as a sine wave, then we can use Equa- tion 2 to describe circuit performance. VOUT (t, D) = (D/128-1) × A sin ( ωt) (2) where ω = 2 πf, A = sine wave amplitude, and D = decimal input code. This transfer characteristic Equation 2 lends itself to amplitude and phase control of the incoming signal VIN. When the DAC is loaded with all zeros, the output sine wave is shifted by 180 ° with respect to the input sine wave. This powerful multiplying capability can be used for a wide variety of modulation, wave- form adjustment and amplitude control. SIGNAL INPUTS (VINA, B, C, D, E, F, G, H) The eight independent VIN inputs have a constant input- resistance nominal value of 19 k Ω as specified in the electrical characteristics table. These signal-inputs are designed to receive not only dc, but ac input voltages. The signal-input voltage range can operate to within one volt of either supply. That is, the operating input-voltage-range is: VSS + 1 V < VINx < (VDD – 1 V) (3) DAC OUTPUTS (VOUTA, B, C, D, E, F, G, H) The eight D/A converter outputs are fully buffered by the AD8842’s internal amplifier. This amplifier is designed to drive up to 1 k Ω loads in parallel with 100 pF. However, in order to minimize internal device power consumption, it is recom- mended whenever possible to use larger values of load resis- tance. The amplifier output stage can handle shorts to GND; however, care should be taken to avoid continuous short circuit operation. The low output impedance of the buffers minimizes crosstalk between analog input channels. A graph (Figure 11) of analog crosstalk between channels is provided in the typical perfor- mance characteristics section. At 100 kHz 70 dB of channel-to- channel isolation exists. It is recommended to use good circuit layout practice such as guard traces between analog channels and power supply bypass capacitors. A 0.01 µF ceramic in paral- lel with a 1 µF–10 µF tantalum capacitor provides a good power supply bypass for most frequencies encountered. DIGITAL INTERFACING The four digital input pins (CLK, SDI, LD, PR) of the AD8842 were designed for TTL and 5 V CMOS logic compatibility. The SDO output pin offers good fanout in CMOS logic applications and can easily drive several AD8842s. The Logic Contro Input Truth Table II describes how to shift data into the internal 12-bit serial input register. Note that the CLK is a positive-edge sensitive input. If mechanical switches are used for breadboard evaluation, they should be debounced by a flipflop or other suitable means. The basic three-wire serial data interface setup is shown in Figure 30. Figure 30. Basic Three-Wire Serial Interface The required address plus data input format is defined in the se- rial input decode Table I. Note there are 8 address states that result in no operation (NOP) or activity in the AD8842 when the positive edge triggered load-strobe (LD) is activated. This NOP can be used in cascaded applications where only one DAC out of several packages needs updating. The packages not re- quiring data changes would receive the NOP address, that is, all zeros. It takes 12 clocks on the CLK pin to fully load the serial- input shift-register. Data on the SDI input pin is subject to the timing diagram (Figure 3) data setup and data hold time re- quirements. After the twelfth clock pulse the processor needs to activate the LD strobe to have the AD8842 decode the serial- register contents and update the target DAC register with the 8- bit data word. This needs to be done before the thirteenth positive clock edge. The timing requirements are provided in the electrical characteristic table and in the Figure 3 timing dia- gram. After twelve clock edges, data initially loaded into the shift register at SDI appears at the shift register output SDO. A multiple package interface circuit is shown in Figure 31. In this topology all the devices are clocked with the new data; however, only the decoded package address signal updates the target package LD strobe which is being used as a chip select. AD8842 7 20 17 16 21 19 6 +5V –5V PR SDI CLK LD ZERO VOLTAGE OUTPUT PRESET SERIAL DATA CLOCK LOAD STROBE A |
Numéro de pièce similaire - AD8842AN |
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Description similaire - AD8842AN |
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