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AD5066ARUZ Fiches technique(PDF) 1 Page - Analog Devices |
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AD5066ARUZ Fiches technique(HTML) 1 Page - Analog Devices |
1 / 24 page Fully Accurate, 16-Bit, Unbuffered VOUT, Quad SPI Interface, 2.7 V to 5.5 V nanoDAC in a TSSOP AD5066 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009–2010 Analog Devices, Inc. All rights reserved. FEATURES Low power quad 16-bit nanoDAC, ±1 LSB INL Low total unadjusted error of ±0.1 mV typically Low zero code error of 0.05 mV typically Individually buffered reference pins 2.7 V to 5.5 V power supply Specified over full code range of 0 to 65535 Power-on reset to zero scale or midscale Per channel power-down with 3 power-down functions Hardware LDAC with software LDAC override function CLR Small 16-lead TSSOP function to programmable code APPLICATIONS Process control Data acquisition systems Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources GENERAL DESCRIPTION The AD5066 is a low power, 16-bit quad-channel, unbuffered voltage output nanoDAC® offering relative accuracy specifica- tions of ±1 LSB INL with individual reference pins and can operate from a single 2.7 V to 5.5 V supply. The AD5066 also offers a differential accuracy specification of ±1 LSB DNL. Reference buffers are also provided on-chip. The part uses a versatile 3-wire, low power Schmitt trigger serial interface that operates at clock rates up to 50 MHz and is compatible with standard SPI®, QSPI™, MICROWIRE™, and most DSP interface standards. The AD5066 incorporates a power-on reset circuit that ensures the DAC output powers up to zero scale or midscale and remains there until a valid write to the device takes place. Total unadjusted error for the part is <0.8 mV. Zero code error for the part is 0.05 mV typically. The AD5066 contains a power-down feature that reduces the current consumption of the device to typically 400 nA at 5 V and provides software selectable output loads while in power- down mode. The outputs of all DACs can be updated simultaneously using the hardware LDAC function, with the added functionality of user software selectable DAC channels to update simultaneously. There is also an asynchronous CLR that clears all DACs to a software-selectable code—0 V, midscale, or full scale. PRODUCT HIGHLIGHTS 1. Quad channel available in 16-lead TSSOP, ±1 LSB INL. 2. Individually buffered voltage reference pins. 3. TUE = ±0.8 mV max and zero code error = 0.1 mV max. 4. High speed serial interface with clock speeds up to 50 MHz. 5. Three power-down modes available to the user. 6. Reset to known output voltage (zero scale or midscale). Table 1. Related Devices Part No. Description AD5666 Quad,16-bit buffered DAC,16 LSB INL, TSSOP AD5025/AD5045/AD50651 Dual,12-/14-/16-bit buffered nanoDAC, TSSOP AD5024/AD5044/AD50641 Quad 16-bit nanoDAC, TSSOP AD50621 Single, 16-bit nanoDAC, SOT-23 AD50631 Single, 16-bit nanoDAC, MSOP AD5061 Single,16-bit nanoDAC, ±4 LSB INL, SOT-23 AD5040/AD50601 14-/16-bit nanoDAC, SOT-23 1 ±1 LSB INL FUNCTIONAL BLOCK DIAGRAM INTERFACE LOGIC INPUT REGISTER DIN LDAC GND VDD LDAC VREFA SYNC SCLK AD5066 CLR VOUTA VOUTB VOUTC VOUTD DAC REGISTER DAC A INPUT REGISTER DAC REGISTER DAC B INPUT REGISTER DAC REGISTER DAC C DAC D INPUT REGISTER DAC REGISTER VREFB VREFC VREFD POR POWER-DOWN LOGIC POWER-ON RESET Figure 1. |
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