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TPS54426PWPR Fiches technique(PDF) 7 Page - Texas Instruments

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No de pièce TPS54426PWPR
Description  4.5V to 18V Input, 4-A Synchronous Step-Down SWIFT Converter with Eco-Mode
Download  28 Pages
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI - Texas Instruments

TPS54426PWPR Fiches technique(HTML) 7 Page - Texas Instruments

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(
)
(
)
2
1
-
×
=
=
× ×
IN
OUT
OUT
OUT LL
IN
V
V
V
I
L fsw
V
Tss(ms)=
C6(nF) Vref
Iss( A)
µ
=
C6(nF) 0.765
2
TPS54426
www.ti.com
SLVSAD6C
– AUGUST 2010 – REVISED JULY 2011
OVERVIEW
The TPS54426 is a 4-A synchronous step-down (buck) converter with two integrated N-channel MOSFETs and
auto-skip Eco-mode
™ to improve light lode efficiency. It operates using D-CAP2™ mode control. The fast
transient response of D-CAP2
™ control reduces the output capacitance required to meet a specific level of
performance. Proprietary internal circuitry allows the use of low ESR output capacitors including ceramic and
special polymer types.
DETAILED DESCRIPTION
PWM Operation
The main control loop of the TPS54426 is an adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2
™ mode control. D-CAP2™ mode control combines constant on-time control with
an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low ESR and ceramic output capacitors. It is stable with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. The MOSFET is turned off after the internal
one-shot timer expires. The one-shot timer is set by the converter input voltage, VIN, and the output voltage, VO,
to maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control.
The one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below
the reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the
need for ESR induced output ripple from D-CAP2
™ mode control.
PWM Frequency and Adaptive On-Time Control
TPS54426 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The
TPS54426 runs with a pseudo-constant frequency of 700 kHz by using the input voltage and output voltage to
set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the
output voltage, therefore, when the duty ratio is VOUT/VIN, the frequency is constant.
Auto-Skip Eco-Mode
™ Control
The TPS54426 is designed with Auto-Skip Eco-mode
™ to increase light load efficiency. As the output current
decreases from heavy load condition, the inductor current is also reduced and eventually comes to point that its
rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The rectifying MOSFET is turned off when its zero inductor current is detected. As the load
current further decreases the converter run into discontinuous conduction mode. The on-time is kept almost the
same as is was in the continuous conduction mode so that it takes longer time to discharge the output capacitor
with smaller load current to the level of the reference voltage. The transition point to the light load operation
IOUT(LL) current can be calculated in Equation 1.
(1)
Soft Start and Pre-Biased Soft Start
The soft start function is adjustable. When the EN pin becomes high, 2
μA current begins charging the capacitor
which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during start up.
The equation for the slow start time is shown in Equation 2. VFB voltage is 0.765 V and SS pin source current is
2
μA.
(2)
The TPS54426 contains a unique circuit to prevent current from being pulled from the output during startup if the
output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start
becomes greater than feedback voltage VFB), the controller slowly activates synchronous rectification by starting
the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a
cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter.
This scheme prevents the initial sinking of the pre-bias output, and ensure that the out voltage (VO) starts and
ramps up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to
normal mode operation.
Copyright
© 2010–2011, Texas Instruments Incorporated
7
Product Folder Link(s) :TPS54426


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