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TPIC2603NE Fiches technique(PDF) 5 Page - Texas Instruments |
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TPIC2603NE Fiches technique(HTML) 5 Page - Texas Instruments |
5 / 19 page TPIC2603 6CHANNEL SERIAL INTERFACE LOW SIDE DRIVER SLIS056A − FEBRUARY 1995 − REVISED MARCH 1996 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 switching characteristics, VCC = 5 V, TC = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tw Clock cycle period pulse duration, SCLK See Figure 1 250 555 ns twH(SCLK) Pulse duration, SCLK high See Figure 1 100 248 ns twL(SCLK) Pulse duration, SCLK low See Figure 1 100 248 ns tpd1 Propagation delay from falling edge of CS to SDO valid CS = 0.8 V to SDO low impedance (see Figure 1) 150 300 ns tpd2 Propagation delay from rising edge of CS to SDO 3-state CS = 2 V to SDO 3-state 150 200 ns tpd3 Propagation delay from SCLK to SDO valid CS < 0.8 V 80 172 ns tr(SDO) Rise time of SDO Cload = 200 pF 30 50 ns tf(SDO) Fall time of SDO Cload = 200 pF 30 50 ns t(stb) Short-to-battery/shorted-load/open-load deglitch time See Figures 5 and 6 25 70 100 µs td(on) Turn-on delay time, rising edge of CS to drain 0.4 5 10 td(off) Turn-off delay time, rising edge of CS to drain Vbat = 14 V, R = 30 0.4 5 15 s tr(drain) Rise time of drain terminal Vbat = 14 V, Rload = 30 Ω 0.4 5 10 µs tf(drain) Fall time of drain terminal load 0.4 5 10 f(SCLK) Serial clock frequency 1.8 4 MHz tcyc(ref) Short-to-battery sense cycle time See Figure 5 1.6 4 6.4 ms tw(sense) Short-to-battery sense pulse duration See Figure 5 25 70 100 µs tsu1 Setup to/from the fall edge of CS to the rising edge of SCLK See Figure 1 150 200 ns tsu(SDI) Setup time, SDI to SCLK See Figure 1 25 55 ns th(SDI) Hold time, SDI after SCLK See Figure 1 10 55 ns thermal resistance PARAMETER TEST CONDITIONS MIN MAX UNIT RθJA Junction-to-ambient thermal resistance All outputs with equal power 50 °C RθJC Junction-to-case thermal resistance All outputs with equal power 10 °C |
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Description similaire - TPIC2603NE |
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