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TPIC44L01DBRG4 Fiches technique(PDF) 4 Page - Texas Instruments

No de pièce TPIC44L01DBRG4
Description  4-CHAMMEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI - Texas Instruments

TPIC44L01DBRG4 Fiches technique(HTML) 4 Page - Texas Instruments

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TPIC44L01, TPIC44L02, TPIC44L03
4CHANNEL SERIAL AND PARALLEL LOW SIDE PREFET DRIVER
SLIS062B NOVEMBER 1996 – REVISED AUGUST 2001
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
CS
8
I
Chip select. A high-to-low transition on CS enables SDO, latches fault data into the serial interface, and
refreshes FLT. When CS is high, the fault registers can change fault status. On the falling edge of CS, fault data
is latched into the serial output register and transferred using SDO and SCLK. On a low-to-high transition of
CS, serial data is latched in to the output control register.
DRAIN0
21
I
FET drain inputs. DRAIN0 through DRAIN3 are used for both open-load and short-circuit fault detection at the
DRAIN1
19
g
drain of the external FETs. They are also used for inductive transient protection.
DRAIN2
16
DRAIN3
14
FLT
1
I
Fault flag. FLT is a logic level open-drain output that provides a real-time fault flag for shorted-load/
open-load/over-battery voltage/under-battery voltage faults. The device can be ORed with FLT terminals on
other devices for interrupt handling. FLT requires an external pullup resistor.
GATE0
20
O
Gate drive output. GATE0 through GATE3 outputs are derived from the VBAT supply voltage. Internal clamps
GATE1
18
g
BAT
yg
prevent voltages on these nodes from exceeding the VGS rating on most FETs.
GATE2
17
GATE3
15
GND
13
I
Ground and substrate
IN0
4
I
Parallel gate driver. IN0 through IN3 are real-time controls for the gate predrive circuitry. They are CMOS
IN1
5
gg
g
y
y
compatible with hysteresis.
IN2
6
IN3
7
RESET
22
I
Reset. A high-to-low transition of RESET clears all registers and flags. Gate outputs turn off and the FLT flag
is cleared.
SCLK
11
I
Serial clock. SCLK clocks the shift register. Serial data is clocked into SDI and serial fault data is clocked out
of SDO on the falling edge of the serial clock.
SDI
10
I
Serial data input. Output control data is clocked into the serial register through SDI. A 1 on SDI commands a
particular gate output on and a 0 turns it off.
SDO
9
O
Serial data output. SDO is a 3-state output that transfers fault data to the controlling device. It also passes serial
input data to the next stage for cascaded operation. SDO is taken to a high-impedance state when CS is in a
high state.
VBAT
24
I
Battery supply voltage
VCC
12
I
Logic supply voltage
VCOMPEN
2
I
Fault reference voltage select. VCOMPEN selects the internally generated fault reference voltage (0) or an
external fault reference (1) to be used in the shorted- and open-load fault detection circuitry.
VCOMP
3
I
Fault reference voltage. VCOMP provides an external fault reference voltage for the shorted-load and
open-load fault detection circuitry.


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