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74AVC2T45GS Fiches technique(PDF) 3 Page - NXP Semiconductors |
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74AVC2T45GS Fiches technique(HTML) 3 Page - NXP Semiconductors |
3 / 27 page 74AVC2T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 7 — 8 February 2013 3 of 27 NXP Semiconductors 74AVC2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state 5. Functional diagram 6. Pinning information 6.1 Pinning Fig 1. Logic symbol Fig 2. Logic diagram 001aag577 DIR 1B 2B 7 6 1A 2A 5 2 3 VCC(A) VCC(B) 001aag578 DIR 1B 2B 1A 2A VCC(A) VCC(B) Fig 3. Pin configuration SOT505-2 and SOT765-1 74AVC2T45 VCC(A) VCC(B) 1A 1B 2A 2B GND DIR 001aag579 1 2 3 4 6 5 8 7 Fig 4. Pin configuration SOT833-1, SOT1089, SOT1116 and SOT1203 Fig 5. Pin configuration SOT996-2 74AVC2T45 2B 1B VCC(B) DIR 2A 1A VCC(A) GND 001aag580 36 27 18 45 Transparent top view 001aai261 74AVC2T45 Transparent top view 8 7 6 5 1 2 3 4 VCC(A) 1A 2A GND VCC(B) 1B 2B DIR |
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