Q

I

GND

PWM

ST

REF

D

Bias Supply

Bandgap

Reference

Comparator

+

−

Status

Delay

8

4

5

6

3

2

1

TL4242-Q1

SLVS732E – JULY 2010 – REVISED JULY 2013

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

TOP-SIDE MARKING

–40°C to 105°C

TL4242TDRJRQ1

4242T

–40°C to 125°C

TL4242QKTTRQ1

TL4242Q

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2)

Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

PIN FUNCTIONS

NO.

NAME

DESCRIPTION

DRJ

KTT

Status delay. To set status reaction delay, connect to GND with a capacitor. For no delay, leave

D

5

6

open.

GND

3

4

Ground

NC

7

N/A

No internal connection

PWM

1

2

Pulse-width modulation input. If not used, connect to I.

Q

6

7

Output

REF

4

5

Reference input. Connect to a shunt resistor.

ST

2

3

I

8

1

Input. Connect directly to GND as close as possible to the device with a 100-nF ceramic capacitor.

Thermal

–

–

Solder the thermal pad directly to the PCB. Connect to ground or leave floating

pad

Figure 1. FUNCTIONAL BLOCK DIAGRAM

2

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