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SN74HC138QPWRQ1 Fiches technique(PDF) 1 Page - Texas Instruments |
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SN74HC138QPWRQ1 Fiches technique(HTML) 1 Page - Texas Instruments |
1 / 14 page SN74HC138-Q1 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS533A − AUGUST 2003 − REVISED SEPTEMBER 2008 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Qualified for Automotive Applications D ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) D Targeted Specifically for High-Speed Memory Decoders and Data-Transmission Systems D 2-V to 6-V V CC Operation D Outputs Can Drive Up To 10 LSTTL Loads D Low Power Consumption, 80-µA Max I CC D Typical t pd = 15 ns D ±4-mA Output Drive at 5 V D Low Input Current of 1 µA Max D Incorporate Three Enable Inputs to Simplify Cascading and/or Data Reception description/ordering information The SN74HC138 is designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. The conditions at the binary-select inputs at the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. ORDERING INFORMATION{ TA PACKAGE‡ ORDERABLE PART NUMBER TOP-SIDE MARKING 40 °C to 125°C SOIC − D Tape and reel SN74HC138QDRQ1 HC138Q1 −40 °C to 125°C TSSOP − PW Tape and reel SN74HC138QPWRQ1 HC138Q1 † For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ‡ Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 A B C G2A G2B G1 Y7 GND VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 D OR PW PACKAGE (TOP VIEW) Copyright 2008, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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