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TCA8424 Fiches technique(PDF) 4 Page - Texas Instruments

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No de pièce TCA8424
Description  Low-Voltage 8x16 Keyboard Scanner with HID over I2C Compliant Interface
Download  30 Pages
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI - Texas Instruments

TCA8424 Fiches technique(HTML) 4 Page - Texas Instruments

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Non-Volatile
Memory
Registers
(volatile)
HID Descriptor
(30 bytes)
Report Descriptor
(194 bytes)
Keyboard map
(256 bytes)
Report Ids
Usage Codes
Function Key Location
(32 bytes)
Input Register
(8 bytes)
Output Register
(1 bytes)
Command Register
(2 bytes)
Data Register
(2 bytes)
Key scan
Logic
Core Logic
and
internal
registers
I C buffers
and Logic
2
LEDs
Interrupt
SDA
SCL
Rows 0 - 15
TCA8424
SCDS341 – MARCH 2013
www.ti.com
SIMPLIFIED BLOCK DIAGRAM
I
2C INTERFACE
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to VCC through a pull-up resistor. Data transfer may be initiated only when the bus is not busy.
I2C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on
the SDA input/output, while the SCL input is high. After the Start condition, the device address byte is sent, most
significant bit (MSB) first, including the data direction bit (R/W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA
input/output during the high of the ACK-related clock pulse.
On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (Start or Stop). A Stop condition, a low-to-high transition on the SDA input/output while the SCL input
is high, is sent by the master.
Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period. When a
slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the master must
generate an ACK after each byte that it receives from the slave transmitter. Setup and hold times must be met to
ensure proper operation.
4
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