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AM7996DCTR Fiches technique(PDF) 4 Page - Advanced Micro Devices

No de pièce AM7996DCTR
Description  IEEE 802.3/Ethernet/Cheapernet Transceiver
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Fabricant  AMD [Advanced Micro Devices]
Site Internet  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM7996DCTR Fiches technique(HTML) 4 Page - Advanced Micro Devices

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Am7996
PIN DESCRIPTION
Attachment Unit Interface (AUI)
Dl+, Dl–
Receive Line Output (Differential Outputs)
This pair is intended to operate into terminated 78
transmission lines. Signals at RXT meeting bandwidth
requirements and carrier sense levels are outputted at
Dl
±. Signaling at Dl ± meets requirements of
IEEE 802.3, Rev. D.
Cl+, Cl–
Collision Line Output (Differential Outputs)
This pair is intended to operate into terminated 78
transmission lines. Signal Quality Error (SQE), de-
tected at DO
± inputs (excessive transmissions) or RXT
input (during a collision), outputs the 10 MHz internal
oscillator signal to the AUI interface. For proper compo-
nent values at COLL OSC, signaling at Cl
± meets re-
quirements of IEEE 802.3, Rev. D.
DO+, DO–
Transmit Input (Differential Inputs)
A pair of internally biased line receivers consisting of a
squelch detect receiver with offset and noise filtering
and a data receiver with zero offset for data signal pro-
cessing. Signals meeting squelch requirements are
waveshaped and output at TXT.
Coaxial Media Interface (TAP)
RXT
Media Signal Receiver Input (Input)
RXT connects to the media through a 4:1 attenuator of
100 k
Ω total resistance (25 kΩ and 75 kΩ in series).
Return for the attenuator is V
COL. RXT is an analog
input with internal AC coupling for Manchester data sig-
nals and direct coupling for Carrier Detect and SQE av-
erage level detection. Signals at RXT meeting carrier
squelch enable data to the Dl
± outputs. Data signals
are AC coupled to Dl
± with a 150 ns time constant,
high-pass filter. Signals meeting SQE levels enable
COLL OSC frequency to Cl
± outputs.
TXT
Tap Node Driver (Input/Output)
A controlled bandwidth current source and sense am-
plifier. This l/O port is to be connected to the media
through an isolation network and a low-pass filter. Sig-
nals meeting DO
± squelch and jabber timing require-
ments are output at TXT as a controlled rise and fall
time current pulse. When operated into a double termi-
nated 50
Ω transmission line, signaling meets
IEEE 802.3, Rev. D recommendations for amplitude,
pulse-width distortion, rise and fall times, and harmonic
content. The sense amplifier monitors TXT faults and
inhibits transmission.
Global Signals
VC
REF
Timing Reference Set (Input)
VC
REF is a compensated voltage reference input with
respect to V
EE. When a resistor is connected between
VC
REF and VEE, then internal transmit and receive
squelch timing, SQE oscillator frequency, and receive
and SQE output drive levels are set. SQE frequency
set is also determined by components connected be-
tween V
CC1 and COLL OSC.
SQE TEST
Signal Quality Error Test Enable (Input)
The SQE Test function is enabled by connecting the
SQE TEST pin to V
EE and disabled by connecting to VCC.
V
TX+, VTX–
Tap Node Driver Current Set (Inputs)
A reference input for transmission level and external re-
dundant jabber. Transmit level is set by an external re-
sistor between V
TX+ and VTX– (for an 80 mA peak level,
R = 9.09
Ω). V
TX– may be operated between VEE and
V
EE + 1 V. When the voltage at VTX– goes more positive
than V
EE + 2 V, TXT is disabled and an SQE message
is output at the Cl pair.
TAP SHIELD
Low-Noise Media Cable Return (Input)
This input is the return for V
COL reference and the re-
ceive signal from the media. External connection is to
a positive power supply.
V
COL
SQE Reference Voltage (Bias Supply)
SQE sense voltage and RXT input amplifier reference.
An internally set analog reference for SQE level and data
signal set at –1.600 V nominal with a source resistance
of 150
Ω nominal. This reference should be filtered with
respect to TAP SHIELD (see Applications section for ad-
justing threshold levels for other applications).
COLL OSC
SQE Timing Set (Input)
Timing input for SQE oscillator. For a properly set input
at VC
REF, SQE oscillator period is set at 2.1RC. For a
10 MHz SQE oscillator frequency, R should be 1 k
Ω and
C 47 pF, including interconnect and device capacitance.
V
CC1
Positive Logic Supply
V
CC2
SQE Timing Reference (Positive Supply Voltage)
Timing reference return for SQE oscillator and analog
signal ground.
V
EE
Negative Logic Supply and IC Substrate


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