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AM29F080B-120ECB Fiches technique(PDF) 11 Page - Advanced Micro Devices |
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AM29F080B-120ECB Fiches technique(HTML) 11 Page - Advanced Micro Devices |
11 / 37 page Am29F080B 11 P R E L I M I NARY Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to the Command Defi- nitions table). In addition, the following hardware data protection measures prevent accidental erasure or pro- gramming, which might otherwise be caused by spuri- ous system level signals during VCC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than VLKO, the device does not ac- cept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent uninten- tional writes when VCC is greater than VLKO. Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up. |
Numéro de pièce similaire - AM29F080B-120ECB |
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Description similaire - AM29F080B-120ECB |
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