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AM28F010A-120PC Fiches technique(PDF) 1 Page - Advanced Micro Devices |
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AM28F010A-120PC Fiches technique(HTML) 1 Page - Advanced Micro Devices |
1 / 35 page FINAL Publication# 16778 Rev: D Amendment/+2 Issue Date: May 1998 Am28F010A 1 Megabit (128 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory with Embedded Algorithms DISTINCTIVE CHARACTERISTICS s High performance — Access times as fast as 70 ns s CMOS low power consumption — 30 mA maximum active current — 100 µA maximum standby current — No data retention power consumption s Compatible with JEDEC-standard byte-wide 32-pin EPROM pinouts — 32-pin PDIP — 32-pin PLCC — 32-pin TSOP s 100,000 write/erase cycles minimum s Write and erase voltage 12.0 V ±5% s Latch-up protected to 100 mA from –1 V to VCC +1 V s Embedded Erase Electrical Bulk Chip Erase — 5 seconds typical chip erase, including pre-programming s Embedded Program — 14 µs typical byte program, including time-out — 4 seconds typical chip program s Command register architecture for microprocessor/microcontroller compatible write interface s On-chip address and data latches s Advanced CMOS flash memory technology — Low cost single transistor memory cell s Embedded algorithms for completely self-timed write/erase operations GENERAL DESCRIPTION The Am28F010A is a 1 Megabit Flash memory orga- nized as 128 Kbytes of 8 bits each. AMD’s Flash memo- ries offer the most cost-effective and reliable read/write non-volatile random access memory. The Am28F010A is packaged in 32-pin PDIP, PLCC, and TSOP versions. It is designed to be reprogrammed and erased in-system or in standard EPROM programmers. The Am28F010A is erased when shipped from the factory. The standard Am28F010A offers access times of as fast as 70 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention, the device has separate chip enable (CE#) and output enable (OE#) controls. AMD’s Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The Am28F010A uses a command register to manage this functionality. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility. The Am2 8 F01 0 A is c o mpat ible wit h t he AMD Am28F256A, Am28F512A, and Am28F020A Flash memories. All devices in the Am28Fxxx family follow the JEDEC 32-pin pinout standard. In addition, all devices within this family that offer Embedded Algorithms use the same command set. This offers designers the flexi- bility to retain the same device footprint and command set, at any density between 256 Kbits and 2 Mbits. AMD’s Flash technology reliably stores memory con- tents even after 100,000 erase and program cycles. The AMD cell is designed to optimize the erase and program- ming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal elec- tric fields for erase and programming operations pro- duces reliable cycling. The Am28F010A uses a 12.0 ±5% V PP input to perform the erase and program- ming functions. The highest degree of latch-up protection is achieved with AMD’s proprietary non-epi process. Latch-up pro- tection is provided for stresses up to 100 mA on address and data pins from –1 V to VCC +1 V. AMD’s Flash technology combines years of EPROM and EEPROM experience to produce the highest levels of q ua lity, re lia bility, an d cost e ffe ctiven ess. The Am28F010A electrically erases all bits simultaneously using Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the EPROM pro- gramming mechanism of hot electron injection. |
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