 |
Moteur de recherche de fiches techniques de composants électroniques |
|
|
Moteur de recherche de fiches techniques de composants électroniques |
|
AM186ER-40VIW Fiches technique(PDF) 30 Page - Advanced Micro Devices |
|
||||||||||||||||||||||||||||||
AM186ER-40VIW Fiches technique(HTML) 30 Page - Advanced Micro Devices |
|
|
30 / 112 page  30 Am186TMER and Am188TMER Microcontrollers Data Sheet DRAF T PIN DESCRIPTIONS Pins Used by Emulators The following pins are used by emulators: A19–A0, AO15–AO8, AD7–AD0, ALE, BHE/ADEN (on the Am186ER microcontroller), CLKOUTA, RFSH2/ADEN (on the Am188ER microcontroller), RD, S2, S1/IMDIS, S0/SREN, S6/CLKSEL1, and UZI/CLKSEL2. Emu la to rs re qu ire th at S6/C LKSEL1 and UZI / CLKSEL2 be configured in their normal functionality, that is, as S6 and UZI. If BHE/ADEN (on the Am186ER microcontroller) or RFSH2/ADEN (on the Am188ER microcontroller) is held Low during the rising edge of RES, S6 and UZI are configured in their normal func- tionality and cannot be programmed as PIOs. A19–A0 (A19/PIO9, A18/PIO8, A17/PIO7) Address Bus (output, three-state, synchronous) These pins supply nonmultiplexed memory or I/O ad- dresses to the system one-half of a CLKOUTA period earlier than the multiplexed address and data bus (AD15–AD0 on the Am186ER microcontroller or AO15–AO8 and AD7–AD0 on the Am188ER microcon- troller). During a bus hold or reset condition, the ad- dress bus is in a high-impedance state. AD7–AD0 Address and Data Bus (input/output, three-state, synchronous, level-sensitive) These time-multiplexed pins supply partial memory or I/O addresses, as well as data, to the system. AD7– AD0 supply the low-order 8 bits of an address to the system during the first period of a bus cycle (t1). On a write, these pins supply data to the system during the remaining periods of that cycle (t2, t3, and t4). On a read, these pins latch data at the end of t3. Also, if S0/SREN (show read enable) was pulled Low during reset or if the SR bit is set in the Internal Memory Chip Select (IMCS) Register, these pins supply the data read from internal memory during t3 and t4. On the Am186ER microcontroller, AD7–AD0 combine with AD15–AD8 to form a complete multiplexed ad- dress and 16-bit data bus. On the Am188ER microcontroller, AD7–AD0 combine with AO15–AO8 to form a complete multiplexed ad- dress bus while AD7–AD0 is the 8-bit data bus. The address phase of these pins can be disabled. See the ADEN description with the BHE/ADEN pin. When WLB is negated, these pins are three-stated during t2, t3, and t4. During a bus hold or reset condition, the address and data bus are in a high-impedance state. During a power-on reset, the address and data bus pins (AD15–AD0 for the Am186ER microcontroller, AO15–AO8 and AD7–AD0 for the Am188ER microcon- troller) can also be used to load system configuration information into the internal reset configuration regis- ter. The system information is latched on the rising edge of RES. AD15–AD8 (Am186™ER Microcontroller) Address and Data Bus (input/output, three-state, synchronous, level-sensitive) These time-multiplexed pins supply partial memory or I/O addresses, as well as data, to the system. AD15– AD8 supply the high-order 8 bits of an address to the system during the first period of a bus cycle (t1). On a write, these pins supply data to the system during the remaining periods of that cycle (t2, t3, and t4). On a read, these pins latch data at the end of t3. Also, if S0/SREN (show read enable) was pulled Low during reset or if the SR bit is set in the Internal Memory Chip Select (IMCS) Register, these pins supply the data read from internal memory during t3 and t4. On the Am186ER microcontroller, AD15–AD8 combine with AD7–AD0 to form a complete multiplexed address and 16-bit data bus. The address phase of these pins can be disabled. See the ADEN description with the BHE/ADEN pin. When WHB is negated, these pins are three-stated during t2, t3, and t4. During a bus hold or reset condition, the address and data bus is in a high-impedance state. During a power-on reset, the address and data bus pins (AD15–AD0 for the Am186ER microcontroller, AO15–AO8 and AD7–AD0 for the Am188ER microcon- troller) can also be used to load system configuration information into the internal reset configuration regis- ter. The system information is latched on the rising edge of RES. AO15–AO8 (Am188™ER Microcontroller) Address-Only Bus (output, three-state, synchronous, level-sensitive) On the Am188ER microcontroller, the address-only bus (AO15–AO8) contains valid high-order address bits from bus cycles t1–t4. These outputs are three-stated during a bus hold or reset. On the Am188ER microcontroller, AO15–AO8 combine with AD7–AD0 to form a complete multiplexed address bus while AD7–AD0 is the 8-bit data bus. On the Am188ER microcontroller during a power-on reset, the AO15–AO8 and AD7–AD0 pins can also be used to load system configuration information into an internal register for later use. |
Numéro de pièce similaire - AM186ER-40VIW |
|
Description similaire - AM186ER-40VIW |
|
|
Lien URL |
| Politique de confidentialité |
| ALLDATASHEET.FR |
| ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
French ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
