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AM186ER-25KCW Fiches technique(PDF) 49 Page - Advanced Micro Devices |
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AM186ER-25KCW Fiches technique(HTML) 49 Page - Advanced Micro Devices |
49 / 112 page Am186TMER and Am188TMER Microcontrollers Data Sheet 49 DRAF T CHIP-SELECT UNIT The Am186ER and Am188ER microcontrollers contain logic that provides programmable chip-select genera- tion for both memories and peripherals. The logic can be programmed to provide external ready and wait- state generation and latched address bits A1 and A2. The chip-select lines are active for all memory and I/O cycles in their programmed areas, whether they are generated by the CPU or by the integrated DMA unit. Chip-Select Timing The timing for the UCS and LCS outputs is modified from the original Am186 microcontroller. These outputs now assert in conjunction with the nonmultiplexed ad- dress bus for normal memory timing. To enable these outputs to be available earlier in the bus cycle, the num- ber of programmable memory size selections has been reduced. Ready and Wait-State Programming The Am186ER and Am188ER microcontrollers can be programmed to sense a ready signal for each of the ex- ternal peripheral or memory chip-select lines. The ex- ternal ready signal can be either the ARDY or SRDY signal as shown in Figure 11. For diagrams of the syn- chronous ready waveforms and asynchronous ready waveforms, refer to page 97. Each external chip-select control register (UMCS, LMCS, MMCS, PACS, and MPCS) contains a single-bit field that determines whether the external ready signal is required or ig- nored. The internal memory ignores the external ready signal. The number of wait states to be inserted for each ac- cess to an external peripheral or memory region is pro- grammable. The chip-select control registers for UCS, LCS, MCS3–MCS0, PCS6, and PCS5 contain a two-bit field that determines the number of wait states from zero to three to be inserted. PCS3–PCS0 use three bits to provide additional values of 5, 7, 9, and 15 wait states. The chip-select control register for internal memory always specifies no wait states. When external ready is required, internally pro- grammed wait states will always complete before exter- nal ready can terminate or extend a bus cycle. For example, if the internal wait states are set to insert two wait states, the processor samples the external ready pin during the first wait cycle. If external ready is as- serted at that time, the access completes after six cy- cles (four cycles plus two wait states). If external ready is not asserted during the first wait state, the access is extended until ready is asserted, which is followed by one more wait state followed by t4. Figure 11. ARDY and SRDY Synchronization Logic Diagram D Q Rising Edge D Q Falling Edge DQ Falling Edge Bus Ready SRDY CLKOUTA ARDY |
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