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AD7739BRU Fiches technique(PDF) 8 Page - Analog Devices |
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AD7739BRU Fiches technique(HTML) 8 Page - Analog Devices |
8 / 32 page AD7739 Data Sheet Rev. A | Page 8 of 32 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 5. Pin Configuration (24-Lead TSSOP) Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 SCLK Serial Clock. Schmitt triggered logic input. An external serial clock is applied to this input to transfer serial data to or from the AD7739. 2 MCLKIN Master Clock Signal for the ADC. This can be provided in the form of a crystal/resonator or external clock. A crystal/resonator can be tied across the MCLKIN and MCLKOUT pins. Alternatively, MCLKIN can be driven with a CMOS compatible clock and MCLKOUT can be left unconnected. 3 MCLKOUT Master Clock Signal for the ADC. When the master clock for the device is a crystal/ resonator, the crystal/resonator is connected between MCLKIN and MCLKOUT. If an external clock is applied to the MCLKIN, MCLKOUT provides an inverted clock signal or can be switched off to reduce the device power consumption. MCLKOUT can drive one CMOS load. 4 CS Chip Select. Active low Schmitt triggered logic input with an internal pull-up resistor. With this input hardwired low, the AD7739 can operate in its 3-wire interface mode using SCLK, DIN, and DOUT. CS can be used to select the device in systems with more than one device on the serial bus. It can also be used as an 8-bit frame synchronization signal. 5 RESET Schmitt Triggered Logic Input. Active low input that resets the control logic, interface logic, digital filter, analog modulator, and all on-chip registers of the part to power-on status. Effectively, everything on the part except the clock oscillator is reset when the RESET pin is exercised. 6 AVDD Analog Positive Supply Voltage, 5 V to AGND Nominal. 7 AINCOM/P0 Analog Inputs Common Terminal/Digital Output. The function of this pin is determined by the P0 DIR bit in the I/O port register; the digital value can be written as the P0 bit in the I/O port register. The digital voltage is referenced to analog supplies. When configured as an input (P0 DIR bit set to 1), the single-ended analog inputs 0 to 7 (AIN0 to AIN7) can be referenced to the voltage level of this pin. 8 SYNC/P1 SYNC/Digital Input/Digital Output. The pin direction is determined by the P1 DIR bit; the digital value can be read/written as the P1 bit in the I/O port register. When the sync bit in the I/O port register is set to 1, then the SYNC/P1 pin can be used to synchronize the AD7739 modulator and digital filter with other devices in the system. The digital voltage is referenced to the analog supplies. When configured as an input, tie the pin high or low. 9 to 16 AIN0 to AIN7 Analog Inputs. 17 REFIN(+) Positive Terminal of the Differential Reference Input. REFIN(+) voltage potential can lie anywhere between AVDD and AGND. In normal circuit configuration, connect this pin to a 2.5 V reference voltage. 18 REFIN(−) Negative Terminal of the Differential Reference Input. REFIN(−) voltage potential can lie anywhere between AVDD and AGND. In normal circuit configuration, connect this pin to a 0 V reference voltage. TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 AD7739 AIN4 AIN5 AIN6 AIN7 SYNC/P1 SCLK MCLKIN MCLKOUT CS AINCOM/P0 AVDD RESET AIN3 AIN2 AIN1 AIN0 REFIN(+) DGND DVDD DIN DOUT REFIN(–) AGND RDY 03742-0-011 |
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