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AD8116JSTZ Fiches technique(PDF) 6 Page - Analog Devices |
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AD8116JSTZ Fiches technique(HTML) 6 Page - Analog Devices |
6 / 29 page AD8116 –5– REV. B Table II. Operation Truth Table Control Lines CE UPDATE CLK DATA IN DATA OUT RESET Operation/Comment 1 X X X X 1 No change in logic. 01 f Data i Data i-80 1 The data on the DATA IN line is loaded into the serial register. The first bit clocked into the serial register appears at DATA OUT 80 clocks later. 0 0 X X X 1 Data in the serial shift register transfers into the parallel latches that control the switch array. Latches are transparent. X X X X X 0 Asynchronous operation. All outputs are disabled. Remainder of logic is unchanged. 256 DECODE SWITCH MATRIX LE D LE D LE D LE D LE D LE D LE D LE D LE D LE D LE D LE D EN 0 LSB 12 3 EN MSB 0 LSB 12 3 EN MSB 0 CLR QQQQQQ CLR CLR Q Q QQ QQ 54 3 2 1 0 79 78 77 76 75 74 OUT14 OUT15 OUT15 OUT15 OUT15 OUT15 OUT0 OUT0 OUT0 OUT0 OUT0 OUT1 DDDDD D QQQQQ Q CLK CLK CLK CLK CLK CLK DDDDD D QQQQQ Q CLK CLK CLK CLK CLK CLK OUTPUT CH CH BIT # SERIAL BIT # DATA IN DATA OUT RESET UPDATE CE CLK OUTPUT ENABLE 16 Figure 4. Logic Diagram |
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