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TPS65301-Q1 Fiches technique(PDF) 7 Page - Texas Instruments |
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TPS65301-Q1 Fiches technique(HTML) 7 Page - Texas Instruments |
7 / 38 page TPS65301-Q1 www.ti.com SLVSC10B – OCTOBER 2013 – REVISED DECEMBER 2013 PIN DESCRIPTIONS (continued) PIN NUMBER I/O DESCRIPTION NAME PWP RHF Active-low, open-drain reset output connected to external bias voltage through a resistor. This output is asserted high after the preregulator, 3.3-V, and 1.2-V regulator outputs are regulating and the delay nRST 23 21 O timer has expired. Also, output is asserted low if any one of these three supplies is out of the set regulation, this threshold is internally set. Power ground pin, must be electrically connected to exposed pad on PCB for proper thermal PGND 24 22 O performance Thermal – – – Electrically connect to ground and solder to ground plane of PCB for thermal efficiency pad Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: TPS65301-Q1 |
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