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AD526JNZ Fiches technique(PDF) 9 Page - Analog Devices |
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AD526JNZ Fiches technique(HTML) 9 Page - Analog Devices |
9 / 14 page AD526 REV. D –9– The specifications on page 3, in combination with Figure 35, give the timing requirements for loading new gain codes. VALID DATA GAIN CODE INPUTS CLK OR CS TC TH TS TC = MINIMUM CLOCK CYCLE TS = DATA SETUP TIME TH = DATA HOLD TIME NOTE: THRESHOLD LEVEL FOR GAIN CODE, CS, AND CLK IS 1.4V. Figure 35. AD526 Timing TIMING AND CONTROL Table I. Logic Input Truth Table Gain Code Control Condition A2 A1 A0 B CLK (CS = 0) Gain Condition XXXX 1 Previous State Latched 0001 0 1 Transparent 0011 0 2 Transparent 0101 0 4 Transparent 0111 0 8 Transparent 1 X X 1 0 16 Transparent XXX0 0 1 Transparent XXX0 1 1 Latched 0001 1 1 Latched 0011 1 2 Latched 0101 1 4 Latched 0111 1 8 Latched 1 X X 1 1 16 Latched NOTE: X = Don’t Care. DIGITAL FEEDTHROUGH With either CS or CLK or both held high, the AD526 gain state will remain constant regardless of the transitions at the A0, A1, A2 or B inputs. However, high speed logic transitions will un- avoidably feed through to the analog circuitry within the AD526 causing spikes to occur at the signal output. This feedthrough effect can be completely eliminated by operat- ing the AD526 in the transparent mode and latching the gain code in an external bank of latches (Figure 36). To operate the AD526 using serial inputs, the configuration shown in Figure 36 can be used with the 74LS174 replaced by a serial-in/parallel-out latch, such as the 54LS594. OUT FORCE OUT SENSE VOUT 0.1 F –VS 0.1 F +VS +5V VIN 74LS174 1 F B A2 A0 A1 TIMING SIGNAL 16 15 14 13 12 11 10 9 12 34 56 78 + – AD526 16 84 21 GAIN NETWORK A1 A0 CS CLK A2 B LOGIC AND LATCHES Figure 36. Using an External Latch to Minimize Digital Feedthrough |
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