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TPS24751RUVR Fiches technique(PDF) 3 Page - Texas Instruments

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No de pièce TPS24751RUVR
Description  12A eFuse Circuit Protector with Current Monitor
Download  42 Pages
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

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TPS24750
TPS24751
www.ti.com
SLVSC87 – OCTOBER 2013
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
OV
0
16
Input voltage range
SENSE, SET(1), VCC(2)
2.5
18
V
EN, FLTb, GATE (2), PGb, OUT(2), DRAIN(2)
0
18
Sink current
FLTb, PGb
0
2
mA
Source current
IMON
0
1
mA
Resistance
PROG
4.99
500
k
Ω
TIMER
1
nF
External capacitance
GATE(3)
1
µF
Operating junction temperature range, TJ
–40
125
°C
(1)
Do not apply voltage directly to these pins.
(2)
Refer Application section Gate Clamp Diode for additional precaution to be taken for operating voltages >14 V.
(3)
External capacitance tied to GATE should be in series with a resistor no less than 1 k
Ω.
ELECTRICAL CHARACTERISTICS
–40°C
≤ TJ ≤ 125°C, VCC = 12 V, VEN = 3 V, RSET = 191 Ω, RIMON = 5 kΩ, and RPROG = 50 kΩ to GND. All voltages referenced
to GND, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
VCC
UVLO threshold, rising
2.20
2.32
2.45
V
UVLO threshold, falling
2.10
2.22
2.35
V
UVLO hysteresis(1)
0.1
V
Enabled
― IOUT + IVCC + ISENSE
0.5
1
1.4
mA
Supply current
Disabled(1)
― EN = 0 V, IOUT + IVCC + ISENSE
0.45
mA
OUT
1 A
≤ IOUT ≤ 10 A at TJ = 25°C
3
3.5
m
Ω
RON On-resistance
1 A
≤ IOUT ≤ 10 A at TJ =125°C
5
6
m
Ω
Input bias current
VOUT = 12 V
10
16
30
µA
Diode Forward Voltage
VEN = 0V, IOUT = –100 mA, VOUT > VSENSE
0.8
1
V
VEN = 0V, VOUT = 0 V, VDRAIN = 18 V at 25°C
0
1
µA
Leakage Current - DRAIN to OUT
VEN = 0V, VOUT = 0 , VDRAIN = 18 V at 125°C
2
5
µA
Ciss Input Capacitance
2710
3250
pF
Coss Output Capacitance
VGS = 0V, VDRAIN-OUT = 15V, f = 1MHz
635
762
pF
Crss Reverse Transfer Capacitance
48
60
pF
Qg Gate Charge Total (4.5V)
17.5
21.5
nC
VDRAIN-OUT = 15V, IOUT = 20 A
Qg(th) Gate Charge at Vth
4.1
nC
EN
Threshold voltage, falling
1.2
1.3
1.4
V
Hysteresis(1)
50
mV
Input leakage current
0 V
≤ VEN ≤ 30 V
–1
0
1
µA
Turnoff time
EN
↓ to VGATE < 1 V
3
8
25
µs
Deglitch time
EN
8
14
21
µs
Disable delay
EN
↓ to GATE ↓, CGATE = 0, tpff50–90, See Figure 1
0.1
0.4
1.8
µs
Turn-On Delay
COUT = 2.2 uF, VEN ↑ to VOUT ↑, VEN: 0 V to 3 V, VOUT : 90% VCC
800
µs
OV
Threshold voltage, rising
1.25
1.35
1.45
V
Hysteresis(1)
60
mV
Input leakage current
0 V
≤ VOV ≤ 30 V
–1
0
1
µA
Deglitch time
OV rising
0.5
1.2
1.5
µs
(1)
These parameters are provided for reference only and do not constitute part of TI’s published device specifications for purposes of TI’s
product warranty.
Copyright © 2013, Texas Instruments Incorporated
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