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TPS24750RUVR Fiches technique(PDF) 8 Page - Texas Instruments

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No de pièce TPS24750RUVR
Description  12A eFuse Circuit Protector with Current Monitor
Download  42 Pages
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

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TPS24750
TPS24751
SLVSC87 – OCTOBER 2013
www.ti.com
DETAILED PIN DESCRIPTIONS
The following description relies on the typical application diagram shown on the front page of this data sheet, as
well as the functional block diagram in Figure 4.
DRAIN: The drain of the internal pass MOSFET. Connect to a terminal of current sense resistor in the power
path.
EN: Applying a voltage of 1.3 V or more to this pin enables the gate driver. The addition of an external resistor
divider allows the EN pin to serve as an undervoltage monitor. Cycling EN low and then back high resets the
TPS24750, TPS24752 that has latched off due to a fault condition. This pin should not be left floating.
FLTb: This active-low open-drain output pulls low when TPS2475x has remained in current limit long enough for
the fault timer to expire. The TPS24750, TPS24752 operates in latch mode while the TPS24751, TPS27513
operates in retry mode. In latch mode, a fault timeout disables the internal MOSFET and holds FLTb low. The
fault is reset when EN is pulled low or VCC falls under UVLO. In retry mode, a fault timeout first disables the
internal MOSFET, next waits sixteen cycles of TIMER charging and discharging, and finally attempts a restart.
This process repeats as long as the fault persists. In retry mode, the FLTb pin is pulled low whenever the internal
MOSFET is disabled by the fault timer. In a sustained fault, the FLTb waveform becomes a train of pulses. The
FLTb pin will not assert if the internal MOSFET is disabled by EN, OV, overtemperature shutdown, or UVLO.
This pin can be left floating when not used.
GATE: This pin provides gate drive to the internal MOSFET. A charge pump sources 30 µA to enhance the
internal MOSFET. A 13.9 V clamp between GATE and VCC limits the gate-to-source voltage since VVCC is close
to VOUT in normal operation. During start up, a transconductance amplifier regulates the gate voltage of the
internal FET to provide inrush current limiting. The TIMER pin charges timer capacitor CT during the inrush.
Inrush current limiting continues until the V(GATE – VCC) exceeds the Timer Activation Voltage 5.8 V for VVCC = 12
V. Then the TPS2475x enters into circuit breaker mode. In the circuit breaker mode, the current flowing in RSENSE
is compared with the current limit threshold derived from the MOSFET power limit scheme (see the PROG
definition). If the current flowing in RSENSE exceeds the current limit threshold, then the internal pass MOSFET
will be turned off. The GATE pin is disabled by the following three mechanisms:
1. GATE is pulled down by an 11-mA current source when
The fault timer expires during an overload current fault (VIMON > 675 mV)
VEN is below its falling threshold
VVCC drops below the UVLO threshold
VOV is above its rising threshold
2. GATE is pulled down by a 1-A current source for 13.5 µs when a hard output short circuit occurs and V(VCC –
SENSE) is greater than 60 mV, that is, the fast-trip shutdown threshold. After fast-trip shutdown is complete, an
11-mA sustaining current ensures that the internal FET remains off.
3. GATE is discharged by a 20-k
Ω resistor to GND if the chip die temperature exceeds the OTSD rising
threshold.
GATE remains low in latch mode (TPS24750, TPS24752) and attempts a restart periodically in retry mode
(TPS24751, TPS24753).
Connect a capacitor from this pin to GND to control the slew rate of the output voltage at power-on. This pin can
be left floating to obtain a predetermined slew rate on the output.
If used, any capacitor connecting GATE and GND should not exceed 1
μF and it should be connected in series
with a resistor of no less than 1 k
Ω. No external resistor should be directly connected from GATE to GND or from
GATE to OUT.
GND: This pin is connected to system ground.
IMON: A resistor connected from this pin to GND scales the current-limit and power-limit settings, as illustrated in
Figure 4. The voltage present at this pin is proportional to the current flowing through sense resistor RSENSE. This
voltage can be used as a means of monitoring current flow through the system. The value of RIMON can be
calculated from Equation 3. This pin should not have a bypass capacitor or any other load except for RIMON.
8
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Product Folder Links: TPS24750 TPS24751


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