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TPS24750RUV Fiches technique(PDF) 9 Page - Texas Instruments |
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TPS24750RUV Fiches technique(HTML) 9 Page - Texas Instruments |
9 / 42 page SET LIM IMON SENSE 0.675 V R I = R R ´ ´ J(MAX) C(MAX) LIM θJC(MAX) T T P < R - SET LIM PROG SENSE IMON 84375 R P R R R ´ = ´ ´ TPS24750 TPS24751 www.ti.com SLVSC87 – OCTOBER 2013 OUT: This pin is connected to the source of the internal MOSFET inside the chip. It allows the device to measure the drain-to-source voltage across the internal MOSFET. The power good indicator (PGb) relies upon this information, as does the power limiting engine. The OUT pin should be bypassed to GND with a low-impedance ceramic capacitor in the range of 10 nF to 1 μF. Connect all the OUT pins to output capacitors and load. In the presence of cable inductance, the OUT pin should be protected from negative voltage transients by using a clamping/Schottky diode. OV: This pin is used to program the device overvoltage level. A voltage of more than 1.35 V on this pin turns off the internal FET. A resistor divider connected from VCC to this pin provides overvoltage protection for the downstream load. This pin should be tied to GND when not used. PGb: This active low, open-drain output is intended to interface to downstream dc/dc converters or monitoring circuits. PGb pulls low after the drain-to-source voltage of the internal FET has fallen below 150 mV and a 3.4 ms deglitch delay has elapsed. It goes open drain when VDS exceeds 220 mV. PGb assumes high impedance status after a 3.4 ms deglitch delay once VDS of internal FET rises up, resulting from GATE being pulled to GND at the following conditions: • An overload current fault occurs (VIMON > 675 mV) and the fault timer times out. • A hard output short circuit occurs, leading to V(VCC – SENSE) greater than 60 mV, that is, the fast-trip shutdown threshold has been exceeded. • VEN is below its falling threshold. • VVCC drops below the UVLO threshold. • VOV is above its rising threshold. • Die temperature exceeds the OTSD threshold. This pin can be left floating when not used. PROG: A resistor from this pin to GND sets the maximum power permitted in the internal MOSFET during inrush. Do not apply a voltage to this pin. If the constant power limit is not desired, use a PROG resistor of 4.99 k Ω. To set the maximum power, use Equation 1, (1) where PLIM is the allowed power limit of the internal MOSFET. RSENSE is the load current monitoring resistor connected between the VCC pin and the SENSE pin. RPROG is the resistor connected from the PROG pin to GND. Both RPROG and RSENSE are in ohms and PLIM is in watts. PLIM is determined by the maximum allowed thermal stress of internal MOSFET, given by Equation 2, (2) where TJ(MAX) is the maximum desired transient junction temperature and TC(MAX) is the maximum case temperature prior to a start or restart. RӨJC(MAX) is the junction-to-case thermal impedance of the internal pass FET in units of °C/W. Both TJ(MAX) and TC(MAX) are in °C. SENSE: This pin connects to the negative terminal of RSENSE. It provides a means of sensing the voltage across this resistor, as well as a way to monitor the drain-to-source voltage across the internal FET. The current limit ILIM is set by Equation 3. (3) A fast-trip shutdown occurs when V(VCC – VSENSE) exceeds 60 mV. SET: A resistor RSET is connected from this pin to the positive terminal of RSENSE. This resistor scales the current limit and power limit settings. It coordinates with RIMON and RSENSE to determine the current limit value. The value of RSET can be calculated from Equation 3 (see SENSE). Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: TPS24750 TPS24751 |
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