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AKD4527B Fiches technique(PDF) 5 Page - Asahi Kasei Microsystems

No de pièce AKD4527B
Description  EVALUATION BOARD REV.D FOR AK4527B
Download  40 Pages
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Fabricant  AKM [Asahi Kasei Microsystems]
Site Internet  http://www.akm.com
Logo AKM - Asahi Kasei Microsystems

AKD4527B Fiches technique(HTML) 5 Page - Asahi Kasei Microsystems

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ASAHI KASEI
[AKD4527B Rev.D]
<KM063700>
- 5 -
’00/9
PORT3
uP-I/F
1
2
9
10
CSN
CCLK
CDTI
CDTO
n Operation sequence
(1) Set up the power supply lines.
[+12V] (orange jack) = +12
∼ +15V
[-12V] (blue jack) = -12
∼ -15V
[AGND]
(black jack)
= 0V
[DGND]
(black jack)
= 0V
Each supply line should be distributed from the power supply unit.
±12V are supplied to analog interface.
+12V is regulated to +5V and +3.3V by regulators(T1,T2).
+5V is supplied to digital interface, AK4527B and TVDD of AK4112A.
+3.3V is supplied to AVDD and DVDD of AK4112A.
(2) Set up the evaluation mode and jumper pins. (See p.3.)
(3) Connect Optical or BNC connector.
[PORT2] (OPT_IN) : Optical input to RX1 of AK4112A
[J10]
(RX2)
: BNC input to RX1 of AK4112A
(4) Power on.
The AK4527B, AK4112A and AK4353 should be reset once bringing PDN(SW1) “L” upon power-up.
(5) Adjust the interface format
Serial control is needed after the reset by SW1. The default value for interface format of
AK4527B, AK4112A, and AK4353 is “Right justified, 20 bit”, “Left justified, 24 bit”, and “I
2S”, respectively.
The software “4527.exe” packed with the AKD4527B is used for the set-up of the AK4527B.
Evaluation mode 1
: DIF1-0 bit of the AK4527B should be set to “11” .
Evaluation mode 2, 3: DIF1-0 bit of the AK4527B should be set to “10”.
Evaluation mode 4
: AK4112A and AK4527B should be set to adjust the format of DSP.
(6) Set up software.
The control mode of AK4527B and AK4112A is fixed to “serial”.
The AKD4527B can be controlled via the printer port (parallel port) of IBM-AT
compatible PC. Connect PORT3(uP-I/F) with PC by 10-line flat cable
packed with the AKD4527B.
Take care of the direction of connector. There is a mark at pin#1.
The pin layout of PORT3 is as Figure 2.
Figure 2. PORT3 pin layout


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