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ADV7842KBCZ-5P Fiches technique(PDF) 10 Page - Analog Devices

No de pièce ADV7842KBCZ-5P
Description  Dual HDMI Fast Switching Receiver with 12-Bit, 170 MHz Video and Graphics igitizer and 3D Comb Filter Decoder
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

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ADV7842
Rev. B | Page 10 of 28
TIMING DIAGRAMS
SDA
SCL
t5
t3
t4
t8
t6
t7
t2
t1
t3
Figure 3. I2C Timing
t9
LLC
P0 TO P35, HS/CS,
VS/FIELD, FIELD/DE
t11
t12
t10
Figure 4. Pixel Port and Control SDR Output Timing (SDP)
t9
LLC
P0 TO P35, VS/FIELD,
HS/CS, FIELD/DE
t13
t14
t10
Figure 5. Pixel Port and Control SDR Output Timing (CP)
SCLK
LRCLK
I2Sx
LEFT-JUSTIFIED
MODE
I2Sx
RIGHT-JUSTIFIED
MODE
I2Sx
I2S MODE
MSB
MSB – 1
t15
t16
t17
t19
t20
t18
MSB
MSB – 1
LSB
MSB
t19
t20
t19
t20
NOTES
1. THE SUFFIX x REFERS TO 0, 1, 2, AND 3 ENDING PIN NAMES.
2. LRCLK IS A SIGNAL ACCESSIBLE VIA AP5 PIN.
3. I2Sx ARE SIGNALS ACCESSIBLE VIA AP1 TO AP4 PINS.
Figure 6. I2S Timing


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