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AD5024BRUZ-REEL7 Fiches technique(PDF) 15 Page - Analog Devices

No de pièce AD5024BRUZ-REEL7
Description  Fully Accurate, 12-/14-/16-Bit VOUT nanoDAC, Quad, SPI Interface, 4.5 V to 5.5 V in TSSOP
Download  28 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD5024BRUZ-REEL7 Fiches technique(HTML) 15 Page - Analog Devices

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Data Sheet
AD5024/AD5044/AD5064
Rev. F | Page 15 of 28
10
0
–10
–20
–60
10
100
1000
10000
FREQUENCY (kHz)
–30
–40
–50
CH A
CH B
CH C
CH D
3dB POINT
Figure 38. Multiplying Bandwidth
5.0
4.0
3.0
2.0
0
TIME (µs)
1.0
4.5
3.5
2.5
1.5
0.5
VDD = 5V, VREF = 4.096V
TA = 25°C
1/4 SCALE TO 3/4 SCALE
3/4 SCALE TO 1/4 SCALE
OUTPUT LOADED WITH 5kΩ
AND 200pF TO GND
0
2
4
6
8
10
12
14
Figure 39. Typical Output Slew Rate
0.0010
0.0008
0.0006
0.0004
0.0002
0
–0.0002
–0.0004
–0.0006
–0.0008
–25 –20 –15 –10
–5
0
5
10
15
20
25
30
CURRENT (mA)
CODE = MIDSCALE
VDD = 5V, VREF = 4.096V
Figure 40. Typical Output Load Regulation
0.10
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
–25 –20 –15 –10
–5
0
5
10
15
20
25
30
IOUT (mA)
CODE = MIDSCALE
VDD = 5V, VREF = 4.096V
Figure 41. Typical Current Limiting Plot
CH1 50mV CH2 5V
M4µs
A CH2
1.2V
T 8.6%
DAC A 295mV p-p
TA = 25°C
VDD = 5V, VREF = 4.096V
Figure 42. Glitch Upon Entering Power-Down (1 kΩ to GND) from Zero Scale,
No Load
CH1 50mV CH2 5V
M4µs
A CH2
1.2V
T 8.6%
DAC A 200mV p-p
TA = 25°C
VDD = 5V, VREF = 4.096V
SCLK
Figure 43. Glitch Upon Entering Power-Down (1 kΩ to GND) from Zero Scale,
5 kΩ/200 pF Load


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