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AD5024BRUZ-REEL7 Fiches technique(PDF) 9 Page - Analog Devices

No de pièce AD5024BRUZ-REEL7
Description  Fully Accurate, 12-/14-/16-Bit VOUT nanoDAC, Quad, SPI Interface, 4.5 V to 5.5 V in TSSOP
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD5024BRUZ-REEL7 Fiches technique(HTML) 9 Page - Analog Devices

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Data Sheet
AD5024/AD5044/AD5064
Rev. F | Page 9 of 28
VOUTA
VREFA
VREFB
VOUTC
POR
DIN
GND
VOUTB
VOUTD
VREFC
VREFD
SCLK
CLR
VDD
LDAC
SYNC
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
AD5024/
AD5044/
AD5064
16
15
14
13
12
11
10
9
Figure 7. 16-Lead TSSOP (RU-16) Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
LDAC
LDAC can be operated in two modes, asynchronously and synchronously, as shown in Figure 4. Pulsing
this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows
all DAC outputs to simultaneously update. This pin can also be tied permanently low in standalone mode.
2
SYNC
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes
low, it powers on the SCLK and DIN buffers and enables the shift register. Data is transferred in on the
falling edges of the next 32 clocks. If SYNC is taken high before the 32nd falling edge, the rising edge of
SYNC acts as an interrupt and the write sequence is ignored by the device.
3
VDD
Power Supply Input. These parts can be operated from 4.5 V to 5.5 V, and the supply should be decoupled
with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
4
VREFB
DAC B Reference Input. This is the reference voltage input pin for DAC B.
5
VREFA
DAC A Reference Input. This is the reference voltage input pin for DAC A.
6
VOUTA
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
7
VOUTC
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
8
POR
Power-On Reset. Tying this pin to GND powers up the part to 0 V. Tying this pin to VDD powers up the
part to midscale.
9
VREFC
DAC C Reference Input. This is the reference voltage input pin for DAC C.
10
CLR
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are
ignored. When CLR is activated, the input register and the DAC register are updated with the data
contained in the clear code register—zero, midscale, or full scale. Default setting clears the output to 0 V.
11
VREFD
DAC D Reference Input. This is the reference voltage input pin for DAC D.
12
VOUTD
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
13
VOUTB
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
14
GND
Ground Reference Point for All Circuitry on the Part.
15
DIN
Serial Data Input. This device has a 32-bit shift register. Data is clocked into the shift register on the
falling edge of the serial clock input.
16
SCLK
Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data
can be transferred at rates of up to 50 MHz.


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