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AD50621 Fiches technique(PDF) 7 Page - Analog Devices |
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AD50621 Fiches technique(HTML) 7 Page - Analog Devices |
7 / 24 page AD5066 Rev. A | Page 7 of 24 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 VDD VREFB VOUTC VOUTA VREFA POR 16 15 14 13 12 11 10 9 DIN GND VOUTB VREFC VREFD VOUTD SCLK AD5066 TOP VIEW (Not to Scale) LDAC SYNC CLR Figure 3. Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 LDAC Load DAC. Logic input. This is used to update the DAC register and, consequently, the analog outputs. When tied permanently low, the addressed DAC register is updated on the falling edge of the 32nd clock. If LDAC is held high during the write cycle, the addressed DAC input shift register is updated but the output is held off until the falling edge of LDAC. In this mode, all analog outputs can be updated simultaneously on the falling edge of LDAC. 2 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and enables the shift register. Data is transferred in on the falling edges of the next 32 clocks. If SYNC is taken high before the 32nd falling edge, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the device. 3 V DD Power Supply Input. The AD5066 can be operated from 2.7 V to 5.5 V. Decouple the supply with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. 4 V REFB External Reference Voltage Input for DAC B. 5 V REFA External Reference Voltage Input for DAC A. 6 V OUTA Unbuffered Analog Output Voltage from DAC A. 7 V OUTC Unbuffered Analog Output Voltage from DAC C. 8 POR Power-On Reset Pin. Tying this pin to GND powers the DAC outputs to zero scale on power-up. Tying this pin to V DD powers the DAC outputs to midscale. 9 V REFC External Reference Voltage Input for DAC C. 10 CLR Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored. When CLR is activated, the input register and the DAC register are updated with the data contained in the CLR code register—zero, midscale, or full scale. Default setting clears the output to 0 V. 11 V REFD External Reference Voltage Input for DAC D. 12 V OUTD Unbuffered Analog Output Voltage from DAC D. 13 V OUTB Unbuffered Analog Output Voltage from DAC B. 14 GND Ground Reference Point for All Circuitry on the Part. 15 DIN Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. 16 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz. |
Numéro de pièce similaire - AD50621 |
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Description similaire - AD50621 |
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