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AD5024 Fiches technique(PDF) 19 Page - Analog Devices

No de pièce AD5024
Description  Fully Accurate, 16-Bit, Unbuffered VOUT, Quad SPI Interface, 2.7 V to 5.5 V nanoDAC in a TSSOP
Download  24 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD5024 Fiches technique(HTML) 19 Page - Analog Devices

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AD5066
Rev. A | Page 19 of 24
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the
board. The printed circuit board containing the AD5066 should
have separate analog and digital sections. If the AD5066 is in a
system where other devices require an AGND-to-DGND con-
nection, make the connection at one point only and as close as
possible to the AD5066.
Bypass the power supply to the AD5066 with 10 µF and 0.1 µF
capacitors. The capacitors should be physically as close as
possible to the device, with the 0.1 µF capacitor, ideally, right up
against the device. The 10 µF capacitors are the tantalum bead
type. It is important that the 0.1 µF capacitor has low effective
series resistance and low effective series inductance, typical of
common ceramic types of capacitors. This 0.1 µF capacitor
provides a low impedance path to ground for high frequencies
caused by transient currents due to internal logic switching.
The power supply line should have as large a trace as possible to
provide a low impedance path and reduce glitch effects on the
supply line. Shield the clocks and other fast switching digital
signals from other parts of the board by digital ground. Avoid
crossover of digital and analog signals if possible. When traces
cross on opposite sides of the board, ensure that they run at
right angles to each other to reduce feedthrough effects through
the board. The best board layout technique is the microstrip
technique, where the component side of the board is dedicated
to the ground plane only, and the signal traces are placed on
the solder side. However, this is not always possible with a
2-layer board.
MICROPROCESSOR INTERFACING
AD5066 to Blackfin® ADSP-BF53X Interface
Figure 43 shows a serial interface between the AD5066 and
the Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x
processor family incorporates two dual-channel synchronous
serial ports, SPORT1 and SPORT0, for serial and multipro-
cessor communications. Using SPORT0 to connect to the
AD5066, the setup for the interface is as follows: DT0PRI
drives the DIN pin of the AD5066, TSCLK0 drives the SCLK
of the parts, and TFS0 drives SYNC.
AD5066*
ADSP-BF53x*
SYNC
TFS0
DIN
DT0PRI
SCLK
TSCLK0
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 43. AD5066 to Blackfin ADSP-BF53X Interface
AD5066 to 68HC11/68L11 Interface
Figure 44 shows a serial interface between the AD5066 and the
68HC11/68L11 microcontroller. SCK of the 68HC11/68L11
drives the SCLK of the AD5066, and the MOSI output drives
DIN of the DAC. A port line (PC7) drives the SYNC signal.
AD5066*
68HC11/68L11*
SYNC
PC7
SCLK
SCK
DIN
MOSI
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 44. AD5066 to 68HC11/68L11 Interface
The setup conditions for correct operation of this interface are
as follows: The 68HC11/68L11 is configured with its CPOL bit
as 0, and the CPHA bit as 1. When data is being transmitted to
the DAC, the SYNC line is taken low (PC7). When the 68HC11/
68L11 is configured as described previously, data appearing on
the MOSI output is valid on the falling edge of SCK. Serial data
from the 68HC11/68L11 is transmitted in 8-bit bytes with only
eight falling clock edges occurring in the transmit cycle. Data is
transmitted MSB first. To load data to the AD5066, PC7 is left
low after the first eight bits are transferred, and a second serial
write operation is performed to the DAC. PC7 is taken high at
the end of this procedure.


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