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AD5024 Fiches technique(PDF) 16 Page - Analog Devices

No de pièce AD5024
Description  Fully Accurate, 16-Bit, Unbuffered VOUT, Quad SPI Interface, 2.7 V to 5.5 V nanoDAC in a TSSOP
Download  24 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD5024 Fiches technique(HTML) 16 Page - Analog Devices

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AD5066
Rev. A | Page 16 of 24
The write sequence begins by bringing the SYNC line low.
Bringing the SYNC line low enables the DIN and SCLK input
buffers. Data from the DIN line is clocked into the 32-bit shift
register on the falling edge of SCLK. The serial clock frequency
can be as high as 50 MHz, making the AD5066 compatible with
high speed DSPs. On the 32nd falling clock edge, the last data bit
is clocked in, and the programmed function is executed, that is,
a change in the input register contents (see Table 8) and/or a
change in the mode of operation. At this stage, the SYNC line
can be kept low or be brought high. In either case, it must be
brought high for a minimum of 2 μs (single-channel update, see
the t8 parameter in Table 4) before the next write sequence so
that a falling edge of SYNC can initiate the next write sequence.
Idle SYNC high between write sequences for even lower power
operation of the part.
SYNC Interrupt
In a normal write sequence, the SYNC line is kept low for at
least 32 falling edges of SCLK, and the DAC is updated on the
32nd falling edge. However, if SYNC is brought high before the
32nd falling edge, this acts as an interrupt to the write sequence.
The input shift register is reset, and the write sequence is seen
as invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see Figure 42).
Power-Down Modes
The AD5066 can be configured through software, in one of
four different modes: normal mode (default) and three separate
power-down modes (see Table 9). Any or all DACs can be
powered down. Command 0100 is reserved for the power-
down function (see Table 7). These power-down modes are
software-programmable by setting two bits, Bit DB9 and
Bit DB8, in the input shift register. Table 9 shows how the state
of the bits corresponds to the mode of operation of the device.
Any or all DACs (DAC A to DAC D) can be powered down to
the selected mode by setting the corresponding four bits (DB3,
DB2, DB1, DB0) to 1. See Table 10 for the contents of the input
shift register during power-down/power-up operation.
When Bit DB9 and Bit DB8 in the control register are set to 0,
the part is configured in normal mode with its normal power
consumption of 2.5 mA at 5 V. However, for the three power-
down modes, the supply current falls to 0.4 µA if all the channels
are powered down. Not only does the supply current fall, but
the output pin is also internally switched from the output of the
DAC to a resistor network of known values. This has the advantage
that the output impedance of the part is known while the part
is in power-down mode. There are three different options: the
output is connected internally to GND through either a 1 kΩ or
a 100 kΩ resistor, or it is left open-circuited (three-state). The
output stage is illustrated in Figure 41.
RESISTOR
NETWORK
VOUT
DAC
POWER-DOWN
CIRCUITRY
Figure 41. Output Stage During Power-Down Mode
The bias generator, DAC core, and other associated linear
circuitry are shut down when all channels are powered down.
However, the contents of the DAC register are unaffected when
in power-down mode. The time to exit power-down mode is
typically 2.9 µs (see Figure 27).
Table 9. Modes of Operation
DB9
DB8
Operating Mode
0
0
Normal operation
Power-down modes
0
1
1 kΩ to GND
1
0
100 kΩ to GND
1
1
Three-state
SCLK
DIN
DB31
DB0
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 32ND FALLING EDGE
VALID WRITE SEQUENCE:
OUTPUT UPDATES ON THE 32ND FALLING EDGE
DB31
DB0
SYNC
Figure 42. SYNC Interrupt Facility


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