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AD5024 Fiches technique(PDF) 21 Page - Analog Devices |
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AD5024 Fiches technique(HTML) 21 Page - Analog Devices |
21 / 28 page Data Sheet AD5024/AD5044/AD5064 Rev. F | Page 21 of 28 MODES OF OPERATION There are three main modes of operation: standalone mode where a single device is used, daisy-chain mode for a system that contains several DACs, and power-down mode when the supply current falls to 0.4 µA at 5 V. Standalone Mode The write sequence begins by bringing the SYNC line low. Data from the DIN line is clocked into the 32-bit shift register on the falling edge of SCLK. The serial clock frequency can be as high as 50 MHz, making the AD5024/AD5044/AD5064/AD5064-1 compatible with high speed DSPs. On the 32nd falling clock edge, the last data bit is clocked in and the programmed function is executed, that is, an LDAC-dependent change in DAC register contents and/or a change in the mode of operation. At this stage, the SYNC line can be kept low or be brought high. In either case, it must be brought high for a minimum of 3 µs (single channel, see Table 4, t8 parameter) before the next write sequence so that a falling edge of SYNC can initiate the next write sequence. SYNC should be idled at rails between write sequences for even lower power operation of the part. SYNC Interrupt In a normal write sequence, the SYNC line is kept low for at least 32 falling edges of SCLK, and the DAC is updated on the 32nd falling edge. However, if SYNC is brought high before the 32nd falling edge, this acts as an interrupt to the write sequence. The write sequence is seen as invalid. Neither an update of the DAC register contents nor a change in the operating mode occurs (see Figure 50). Daisy-Chaining For systems that contain several DACs the SDO pin can be used to daisy-chain several devices together and provide serial readback. The daisy-chain mode is enabled through a software executable daisy-chain enable (DCEN) command. Command 1000 is reserved for this DCEN function (see Table 8). The daisy-chain mode is enabled by setting Bit DB1 in the DCEN register. The default setting is standalone mode, where DB1 = 0. Table 10 shows how the state of the bit corresponds to the mode of operation of the device. Table 10. DCEN (Daisy-Chain Enable) Register DB1 DB0 Description 0 X Standalone mode (default) 1 X DCEN mode The SCLK is continuously applied to the shift register when SYNC is low. If more than 32 clock pulses are applied, the data ripples out of the shift register and appears on the SDO line. This data is clocked out on the rising edge of SCLK and is valid on the falling edge. By connecting this line to the DIN input on the next DAC in the chain, a daisy-chain interface is constructed. Each DAC in the system requires 32 clock pulses; therefore, the total number of clock cycles must equal 32N, where N is the total number of devices that are updated. If SYNC is taken high at a clock that is not a multiple of 32, it is considered an invalid frame and the data is discarded. When the serial transfer to all devices is complete, SYNC is taken high. This prevents any further data from being clocked into the shift register. In daisy-chain mode, the LDAC pin cannot be tied permanently low. The LDAC pin must be used in asynchronous LDAC update mode, as shown in Figure 5. The LDAC pin must be brought high after pulsing. This allows all DAC outputs to simulta- neously update. The serial clock can be continuous or a gated clock. A continuous SCLK source can be used only if SYNC can be held low for the correct number of clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must be used, and SYNC must be taken high after the final clock to latch the data. Table 11. 32-Bit Shift Register Contents for Daisy-Chain Enable MSB LSB DB31 to DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 to DB2 DB1 DB0 X 1 0 0 0 X X X X X 1/0 X Don’t cares Command bits (C3 to C0) Address bits (A3 to A0) Don’t cares DCEN register |
Numéro de pièce similaire - AD5024 |
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Description similaire - AD5024 |
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