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SPT8100 Fiches technique(PDF) 2 Page - Fairchild Semiconductor

No de pièce SPT8100
Description  16-BIT, 5 MSPS CMOS A/D CONVERTER
Download  10 Pages
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Fabricant  FAIRCHILD [Fairchild Semiconductor]
Site Internet  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

SPT8100 Fiches technique(HTML) 2 Page - Fairchild Semiconductor

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1/9/02
SPT8100
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
Supply Voltages
AVDD ...................................................................... +6 V
DVDD ..................................................................... +6 V
OVDD ..................................................................... +6 V
Input Voltages
Analog Input ................................. –0.5 V to VDD +0.5 V
CLK Input ............................................................... VDD
AVDD – DVDD .................................................. ±100 mV
Delta between AGND, DGND, and OGND ...... ±100 mV
Output
Digital Outputs .................................................... 10 mA
Temperature
Operating Temperature ........................... –40 to +85 °C
Junction Temperature ...................................... +175 °C
Lead Temperature (soldering 10 seconds) ...... +300 °C
Storage Temperature ............................ –65 to +150 °C
Note 1: Operation at any Absolute Maximum Rating is not implied. See
Electrical Specifications for proper nominal applied conditions in
typical applications.
ELECTRICAL SPECIFICATIONS
TA=TMIN to TMAX, AVDD=DVDD=+5.0 V, OVDD= 3.3 V, ƒS=5 MSPS, 2.5 VPP input span, Gain=0 dB, REXT=1.43 kΩ, unless
otherwise specified.
TEST
TEST
SPT8100
PARAMETERS
CONDITIONS
LEVEL
MIN
TYP
MAX
UNITS
Resolution
15.9
16
Bits
DC Accuracy
Integral Linearity Error (ILE)
V
±1.25
LSB
Differential Linearity Error (DLE)
V
±0.5
LSB
Gain Error1
IV
–7.5
+7.5
%FSR
Offset Error2
IV
–5+5
%FSR
Analog Input (into PGA)
Differential Input Voltage Range
VIN+, VIN
V5
VPPD
Input Capacitance
IV
15
pF
Input Resistance3
PGA Gain = 0 dB
IV
5.5
k
Input Bandwidth4
PGA Gain = 0 dB
V
12
MHz
Input Common Mode Voltage Range
V
1.15
2.40
3.65
V
Programmable Gain Amp
Composite Input-Referred
ƒIN > 300 kHz
Noise Floor
PGA Gain = 0 dB
V
1.4
LSBRMS
PGA Gain = 2.9 dB
V
1.5
LSBRMS
PGA Gain = 5.8 dB
V
1.6
LSBRMS
PGA Gain = 11.8 dB
V
2.0
LSBRMS
PGA Gain = 14.8 dB
V
2.3
LSBRMS
PGA Gain = 17.5 dB
V
2.6
LSBRMS
PGA Gain = 19.5 dB
V
2.8
LSBRMS
PGA Range
V
19.5
dB
PGA Gain Steps3
VI
0,2.9,5.8,11.8,14.8,17.5,19.5
dB
PGA Gain Accuracy
VI
±0.3
dB
Conversion Characteristics
Maximum Conversion Rate
VI
5
MSPS
Pipeline Delay (Latency)5
IV
5.5
Clocks
Reset Pulse Time (RS)
IV
3
Clocks
Reset Calibration Time
FS = 5 MSPS
V
150
ms
References and External Bias
VRT – VRB (Internal Ref)
VI
2.375
2.5
2.625
V
Bias Resistor Range (External)
V
800
1430
2500
VCM Output Voltage
IV
2.275
2.40
2.525
V
VCM Output Current
IV
47
µA
VRT
V
3.45
3.65
3.85
V
VRB
V
0.95
1.15
1.35
V
1
Total gain error of PGA and ADC using internal references.
2
Total offset error of PGA and ADC relative to mid-scale.
3
See table I for input resistance as a function of PGA gain.
4
Input bandwidth is a frequency to which the fundamental energy drops by 3 dB
5
The input is sampled on the falling edge of the clock and is available on the
output after the rising edge of the clock, 5.5 clock cycles later.


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