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TPS54560DDAR Fiches technique(PDF) 2 Page - Texas Instruments

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No de pièce TPS54560DDAR
Description  4.5 V to 60 V Input, 5 A, Step Down DC-DC Converter with Eco-mode
Download  43 Pages
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

TPS54560DDAR Fiches technique(HTML) 2 Page - Texas Instruments

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GND
7
COMP
6
FB
5
SW
8
2
3
4
1
VIN
EN
RT/CLK
BOOT
Thermal
Pad
9
TPS54560
SLVSBN0 – MARCH 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Table 1. ORDERING INFORMATION(1)
TJ
PACKAGE
PART NUMBER(2)
–40°C to 150°C
8 Pin HSOIC
TPS54560DDA
(1)
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2)
The DDA package is also available in tape and reel packaging. Add an R suffix to the device type (TPS54560DDAR).
DEVICE INFORMATION
PIN CONFIGURATION
HSOIC PACKAGE
(TOP VIEW)
PIN FUNCTIONS
PIN
I/O
DESCRIPTION
NAME
NO.
A bootstrap capacitor is required between BOOT and SW. If the voltage on this capacitor is below the
BOOT
1
O
minimum required to operate the high side MOSFET, the output is switched off until the capacitor is
refreshed.
VIN
2
I
Input supply voltage with 4.5 V to 60 V operating range.
Enable pin, with internal pull-up current source. Pull below 1.2 V to disable. Float to enable. Adjust the input
EN
3
I
undervoltage lockout with two resistors. See the Enable and Adjusting Undervoltage Lockout section.
Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage when using an
external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold,
RT/CLK
4
I
a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and
the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is re-
enabled and the operating mode returns to resistor frequency programming.
FB
5
I
Inverting input of the transconductance (gm) error amplifier.
Error amplifier output and input to the output switch current (PWM) comparator. Connect frequency
COMP
6
O
compensation components to this pin.
GND
7
Ground
SW
8
I
The source of the internal high-side power MOSFET and switching node of the converter.
Thermal Pad
9
GND pin must be electrically connected to the exposed pad on the printed circuit board for proper operation.
2
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Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TPS54560


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