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AD7694 Fiches technique(PDF) 5 Page - Analog Devices |
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AD7694 Fiches technique(HTML) 5 Page - Analog Devices |
5 / 28 page AD7986 Rev. B | Page 5 of 28 TIMING SPECIFICATIONS AVDD = DVDD = 2.5 V, BVDD = 5 V, VIO = 1.8 V to 2.7 V, VREF = 4.096 V, TA = −40°C to +85°C, unless otherwise noted.1 Table 4. Parameter Symbol Min Typ Max Unit Conversion Time: CNV Rising Edge to Data Available (Turbo Mode/Normal Mode) t CONV 400/500 ns Acquisition Time t ACQ 100 ns Time Between Conversions (Turbo Mode/Normal Mode) t CYC 500/660 ns CNV Pulse Width (CS Mode) t CNVH 10 ns Data Read During Conversion (Turbo Mode/Normal Mode) t DATA 200/300 ns Quiet Time During Acquisition from Last SCK Falling Edge to CNV Rising Edge t QUIET 20 ns SCK Period (CS Mode) t SCK 9 ns SCK Period (Chain Mode) t SCK 11 ns SCK Low Time t SCKL 3.5 ns SCK High Time t SCKH 3.5 ns SCK Falling Edge to Data Remains Valid t HSDO 2 ns SCK Falling Edge to Data Valid Delay t DSDO 6 ns CNV or SDI Low to SDO D17 MSB Valid (CS Mode) t EN 10 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) t DIS 8 ns SDI Valid Setup Time from CNV Rising Edge t SSDICNV 4 ns SDI Valid Hold Time from CNV Rising Edge (CS Mode) t HSDICNV 0 ns SDI Valid Hold Time from CNV Rising Edge (Chain Mode) t HSDICNV 0 ns SCK Valid Setup Time from CNV Rising Edge (Chain Mode) t SSCKCNV 5 ns SCK Valid Hold Time from CNV Rising Edge (Chain Mode) t HSCKCNV 5 ns SDI Valid Setup Time from SCK Falling Edge (Chain Mode) t SSDISCK 2 ns SDI Valid Hold Time from SCK Falling Edge (Chain Mode) t HSDISCK 3 ns SDI High to SDO High (Chain Mode with Busy Indicator) t DSDOSDI 5 ns 1 See Figure 2 and Figure 3 for load conditions. 500µA IOL 500µA IOH 1.4V TO SDO CL 20pF Figure 2. Load Circuit for Digital Interface Timing 90% VIO 10% VIO VIH1 VIL1 VIL1 VIH1 tDELAY tDELAY 1MINIMUM VIH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS SPECIFICATIONS IN TABLE 3. Figure 3. Voltage Levels for Timing |
Numéro de pièce similaire - AD7694 |
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Description similaire - AD7694 |
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