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AD7397ARU Fiches technique(PDF) 10 Page - Analog Devices |
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AD7397ARU Fiches technique(HTML) 10 Page - Analog Devices |
10 / 12 page AD7396/AD7397 –10– REV. 0 The rail-to-rail output stage provides ±1 mA of output current. The N-channel output pull-down MOSFET shown in Figure 26 has a 35 Ω ON resistance, which sets the sink current capability near ground. In addition to resistive load driving capability, the amplifier has also been carefully designed and characterized for up to 100 pF capacitive load driving capability. REFERENCE INPUT The reference input terminal has a constant input resistance independent of digital code, which results in reduced glitches on the external reference voltage source. The high 2.5 M Ω input resistance minimizes power dissipation within the AD7396/ AD7397 D/A converters. The VREF input accepts input voltages ranging from ground to the positive-supply voltage VDD. One of the simplest applications, which saves an external reference voltage source, is connection of the VREF terminal to the positive VDD supply. This connection results in a rail-to-rail voltage output span maximizing the programmed range. The reference input will accept AC signals as long as they are kept within the supply voltage range, 0 < VREF IN < VDD. The reference bandwidth and integral nonlinearity error performance are plotted in the Typical Performance Characteristics section, see Figures 10 and 13. The ratiometric reference feature makes the AD7396/AD7397 an ideal companion to ratiometric analog-to-digital converters such as the AD7896. POWER SUPPLY The very low power consumption of the AD7396/AD7397 is a direct result of a circuit design optimizing the use of a CBCMOS process. By using the low power characteristics of CMOS for the logic, and the low noise, tight matching of the complemen- tary bipolar transistors, excellent analog accuracy is achieved. One advantage of the rail-to-rail output amplifiers used in the AD7396/AD7397 is the wide range of usable supply voltage. The part is fully specified and tested for operation from +2.7 V to +5.5 V. POWER SUPPLY BYPASSING AND GROUNDING Precision analog products such as the AD7396/AD7397 require a well filtered power source. Since the AD7396/AD7397 oper- ates from a single +3 V to +5 V supply, it seems convenient to simply tap into the digital logic power supply. Unfortunately, the logic supply is often a switch-mode design, which generates noise in the 20 kHz to 1 MHz range. In addition, fast logic gates can generate glitches, hundred of millivolts in amplitude, due to wiring resistance and inductance. The power supply noise gen- erated thereby means that special care must be taken to assure that the inherent precision of the DAC is maintained. Good engineering judgment should be exercised when addressing the power supply grounding and bypassing of the 12-bit AD7396. The AD7396 should be powered directly from the system power supply. Whether or not a separate power supply trace is avail- able generous supply bypassing will reduce supply line-induced errors. Local supply bypassing consisting of a 10 µF tantalum electrolytic in parallel with a 0.1 µF ceramic capacitor is recom- mended in all applications (Figure 27). AD7396 OR AD7397 REF VDD DGND AGND C * DATA CS A/ B LDA LDB *OPTIONAL EXTERNAL REFERENCE BYPASS 0.1 F 10 F + VOUTA VOUTB +2.7V TO +5.5V Figure 27. Recommended Supply Bypassing INPUT LOGIC LEVELS All digital inputs are protected with a Zener-type ESD protec- tion structure (Figure 28) that allows logic input voltages to exceed the VDD supply voltage. This feature can be useful if the user is driving one or more of the digital inputs with a 5 V CMOS logic input-voltage level while operating the AD7396/AD7397 on a +3 V power supply. If this mode of interface is used, make sure that the VOL of the 5 V CMOS meets the VIL input require- ment of the AD7396/AD7397 operating at 3 V. See Figure 16 for a graph for digital logic input threshold versus operating VDD supply voltage. VDD LOGIC IN GND Figure 28. Equivalent Digital Input ESD Protection In order to minimize power dissipation from input-logic levels that are near the VIH and VIL logic input voltage specifications, a Schmitt trigger design was used that minimizes the input-buffer current consumption compared to traditional CMOS input stages. Figure 15 shows a plot of incremental input voltage versus supply current showing that negligible current consump- tion takes place when logic levels are in their quiescent state. The normal crossover current still occurs during logic transi- tions. A secondary advantage of this Schmitt trigger is the pre- vention of false triggers that would occur with slow moving logic transitions when a standard CMOS logic interface or opto- isolators are used. The logic inputs DB11–DB0, A/ B CS, RS, SHDN all contain Schmitt trigger circuits. DIGITAL INTERFACE The AD7396/AD7397 has a double-buffered, parallel-data input. A functional block diagram of the digital section is shown in Figure 25, while Table I contains the truth table for the logic control inputs. The chip select ( CS) and A/B pins control load- ing of data from the data inputs on pins DB11–DB0 into the internal Input Register. The CS active low input places data into the decoded A/ B input register. When CS returns to logic high within the data setup-and-hold time specifications the new value of data in the input register will be latched. See Truth Table for complete set of conditions. New data can only be transferred to the corresponding DAC register when its LDx pin is strobed active low. The LDx inputs are level-sensitive (DAC Registers are transparent latches) and can be tied active low |
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