CDC339

CLOCK DRIVER

WITH 3STATE OUTPUTS

SCAS331 − DECEMBER 1992 − REVISED MARCH 1994

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POST OFFICE BOX 655303

Clock-Distribution and Clock-Generation

Applications

Outputs

− Four Same-Frequency Outputs

− Four Half-Frequency Outputs

Switching Noise

Significantly Reduces Power Dissipation

Small-Outline (DW) and Shrink

Small-Outline (DB) Packages

description

The CDC339 is a high-performance, low-skew clock driver. It is specifically designed for applications requiring

synchronized output signals at both the primary clock frequency and one-half the primary clock frequency. The

four Y outputs switch in phase and at the same frequency as the clock (CLK) input. The four Q outputs switch

at one-half the frequency of CLK.

When the output-enable (OE) input is low and the clear (CLR) input is high, the Y outputs follow CLK and the

Q outputs toggle on low-to-high transitions of CLK. Taking CLR low asynchronously resets the Q outputs to the

low level. When OE is high, the outputs are in the high-impedance state.

The CDC339 is characterized for operation from − 40

°C to 85°C.

FUNCTION TABLE

INPUTS

OUTPUTS

OE

CLR

CLK

Y1−Y4

Q1− Q4

H

X

X

Z

Z

L

LL

L

L

L

LH

H

L

L

HL

L

Q0†

L

H

↑

H

Q0†

† The level of the Q outputs before the

indicated steady-state input conditions were

established.

Copyright

 1994, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

EPIC-

ΙΙB is a trademark of Texas Instruments Incorporated.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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20

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12

11

Y3

GND

Y4

OE

CLR

Q4

GND

Q3

Y2

GND

Y1

CLK

GND

Q1

GND

Q2

DB OR DW PACKAGE

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