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TPS54614PWP Fiches technique(PDF) 9 Page - Texas Instruments

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No de pièce TPS54614PWP
Description  3-V TO 6-V INPUT, 6-A OUTPUT SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETs (SWIFT)
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI - Texas Instruments

TPS54614PWP Fiches technique(HTML) 9 Page - Texas Instruments

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TPS54611, TPS54612
TPS54613, TPS54614
TPS54615, TPS54616
SLVS400C − AUGUST 2001 − REVISED APRIL 2005
www.ti.com
9
PCB LAYOUT
Figure 11 shows a generalized PCB layout guide for the
TPS54311−16
The VIN pins should be connected together on the printed
circuit board (PCB) and bypassed with a low ESR ceramic
bypass capacitor. Care should be taken to minimize the
loop area formed by the bypass capacitor connections, the
VIN pins, and the TPS54311−16 ground pins. The
minimum recommended bypass capacitance is 10-µF
ceramic with a X5R or X7R dielectric and the optimum
placement is closest to the VIN pins and the PGND pins.
The TPS54311−16 has two internal grounds (analog and
power). Inside the TPS54311−16, the analog ground ties
to all of the noise sensitive signals, while the power ground
ties to the noisier power signals. Noise injected between
the two grounds can degrade the performance of the
TPS54311−16, particularly at higher output currents.
Ground noise on an analog ground plane can also cause
problems with some of the control and bias signals. For
these reasons, separate analog and power ground traces
are recommended. There should be an area of ground one
the top layer directly under the IC, with an exposed area for
connection to the PowerPAD. Use vias to connect this
ground area to any internal ground planes. Use additional
vias at the ground side of the input and output filter
capacitors as well. The AGND and PGND pins should be
tied to the PCB ground by connecting them to the ground
area under the device as shown. The only components
that should tie directly to the power ground plane are the
input capacitors, the output capacitors, the input voltage
decoupling capacitor, and the PGND pins of the
TPS54311−16. Use a separate wide trace for the analog
ground signal path. This analog ground should be used for
the timing resistor RT, slow start capacitor and bias
capacitor grounds. Connect this trace directly to AGND
(pin 1).
The PH pins should be tied together and routed to the
output inductor. Since the PH connection is the switching
node, inductor should be located very close to the PH pins
and the area of the PCB conductor minimized to prevent
excessive capacitive coupling.
Connect the boot capacitor between the phase node and
the BOOT pin as shown. Keep the boot capacitor close to
the IC and minimize the conductor trace lengths.
Connect the output filter capacitor(s) as shown between
the VOUT trace and PGND. It is important to keep the loop
formed by the PH pins, Lout, Cout and PGND as small as
practical.
Connect the output of the circuit directly to the VSENSE
pin. Do not place this trace too close to the PH trace. Do
to the size of the IC package and the device pinout, they
will have to be routed somewhat close, but maintain as
much separation as possible while still keeping the layout
compact.
Connect the bias capacitor from the VBIAS pin to analog
ground using the isolated analog ground trace. If a
slow-start capacitor or RT resistor is used, or if the SYNC
pin is used to select 350-kHz operating frequency, connect
them to this trace as well.


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