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TPS7A6633QDGNRQ1 Fiches technique(PDF) 5 Page - Texas Instruments |
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TPS7A6633QDGNRQ1 Fiches technique(HTML) 5 Page - Texas Instruments |
5 / 26 page Vin SI NC CT Vout SO PG GND D Package (Top View) 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 DGN Package (Top View) Vin EN NC CT Vout FB/NC PG GND TPS7A6601-Q1, TPS7A6633-Q1 TPS7A6650-Q1, TPS7A6933-Q1 TPS7A6950-Q1 www.ti.com SLVSBL0B – DECEMBER 2012 – REVISED AUGUST 2013 DEVICE INFORMATION SOIC 8 (TPS7A69xx-Q1) MSOP 8 (TPS7A66xx-Q1) Pin Functions PIN NO. PIN TYPE DESCRIPTION NAME SOIC-D MSOP - DGN CT 4 4 O Reset-pulse delay adjustment. Connecting this pin via a capacitor to GND EN 2 I Enable pin. Standby state when enable pin becomes lower than threshold Feedback pin when using external resistor divider or NC pin when using internal resistor FB/NC 7 I divider GND 5 5 G Ground reference NC 3 3 Not connected pins Output ready. This open-drain pin must connect to Vout via an external resistor. The PG 6 6 O output voltage going below threshold pulls it down. Sense input pin to supervise input voltage. Connect via an external voltage divider SI 2 I connected to Vs and GND Sense output. This open-drain pin must connect to Vout via an external resistor. The SI SO 7 O voltage becoming lower than the threshold pulls it down. Vin 1 1 P Input power-supply voltage Vout 8 8 P Output voltage — Thermal pad for MSOP-DGN package Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: TPS7A6601-Q1 TPS7A6633-Q1 TPS7A6650-Q1 TPS7A6933-Q1 TPS7A6950-Q1 |
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