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TPS40070PWP Fiches technique(PDF) 10 Page - Texas Instruments |
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TPS40070PWP Fiches technique(HTML) 10 Page - Texas Instruments |
10 / 30 page 60 90 150 180 210 270 120 240 4 2 8 6 10 14 12 18 16 20 RKFF − Feedforward Impedance − kΩ UVLOVON fSW = 500 kHz UVLOVOFF 40 60 100 120 140 180 80 160 4 2 8 6 10 14 12 18 16 20 RKFF − Feedforward Impedance − kΩ UVLOVON fSW = 750 kHz UVLOVOFF TPS40070 TPS40071 SLUS582J – DECEMBER 2003 – REVISED APRIL 2009 .................................................................................................................................................. www.ti.com UNDERVOLTAGE LOCKOUT THRESHOLD UNDERVOLTAGE LOCKOUT THRESHOLD vs vs FEEDFORWARD IMPEDANCE FEEDFORWARD IMPEDANCE Figure 6. Figure 7. The programmable UVLO circuit incorporates 20% hysteresis from the start voltage to the shutdown voltage. For example, if the startup voltage is programmed to be 10 V, the controller starts when VDD reaches 10 V and shuts down when VDD falls below 8 V. The maximum duty cycle begins to decrease as the input voltage rises to twice the startup voltage. Below this point, the maximum duty cycle is as specified in the electrical table. Note that with this scheme, the theoretical maximum output voltage that the converter can produce is approximately two times the programmed startup voltage. For design, set the programmed startup voltage equal to or greater than the desired output voltage divided by maximum duty cycle (85% for frequencies 500 kHz and below). For example, a 5-V output converter should not have a programmed startup voltage below 5.9 V. Figure 8 shows the theoretical maximum duty cycle (typical) for various programmed startup voltages At startup, LDRV may pulse high when VDD is in the range of 1 V to 1.25 V and VDD is rising extremely slowly. To minimize these effects, the ramp rate of VDD at startup should be greater than 1 V/ms. 10 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): TPS40070 TPS40071 |
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