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TPS7A6950-Q1 Fiches technique(PDF) 2 Page - Texas Instruments |
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TPS7A6950-Q1 Fiches technique(HTML) 2 Page - Texas Instruments |
2 / 26 page TPS7A6601-Q1, TPS7A6633-Q1 TPS7A6650-Q1, TPS7A6933-Q1 TPS7A6950-Q1 SLVSBL0B – DECEMBER 2012 – REVISED AUGUST 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) MAX UNITS Vin, EN Unregulated input(2) (3)(4) 45 V Vout Regulated output 7 V SI See (2) (3) Vin V CT 25 V FB, SO, PG Vout V ESD Electrostatic Discharge(5) 4 kV TJ Operating ambient temperature range –40 to 150 °C Tstg Storage temperature range –65 to 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to GND (3) Absolute negative voltage on these pins not to go below –0.3 V (4) Absolute maximum voltage, withstand 45 V for 200 ms (5) The human-body model is a 107-pF capacitor discharged through a 1.5-k Ω resistor into each pin. THERMAL INFORMATION TPS7A66xx-Q1 TPS7A69xx-Q1 THERMAL METRIC(1) UNITS MSOP (8 PINS) SOIC (8 PINS) θJA Junction-to-ambient thermal resistance 63.4 113.2 θJCtop Junction-to-case (top) thermal resistance 53.0 59.6 θJB Junction-to-board thermal resistance(2) 37.4 23.4 °C/W ψJT Junction-to-top characterization parameter 3.7 12.8 ψJB Junction-to-board characterization parameter 37.1 52.9 θJCbot Junction-to-case (bottom) thermal resistance 13.5 NA (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. spacer RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN MAX UNITS Vin Unregulated input 4 40 V EN, SI 0 40 V CT 0 20 V Vout 1.5 5.5 V PG, SO, FB Low voltage (I/O) 0 5.5 V TJ Operating junction temperature range –40 150 °C 2 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPS7A6601-Q1 TPS7A6633-Q1 TPS7A6650-Q1 TPS7A6933-Q1 TPS7A6950-Q1 |
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