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AD5379ABC Fiches technique(PDF) 10 Page - Analog Devices |
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AD5379ABC Fiches technique(HTML) 10 Page - Analog Devices |
10 / 29 page AD5379 Rev. B | Page 9 of 28 PARALLEL INTERFACE VCC = 2.7 V to 5.5 V; VDD = 11.4 V to 16.5 V; VSS = −11.4 V to −16.5 V; AGND = DGND = DUTGND = 0 V; VREF(+) = 5 V; VREF(−) = −3.5 V, FIFOEN = 0 V; all specifications TMIN to TMAX, unless otherwise noted. Table 5. Parameter1, 2, 3 Limit at TMIN to TMAX Unit Description t0 4.5 ns min REG0, REG1, address to WR rising edge setup time. t1 4.5 ns min REG0, REG1, address to WR rising edge hold time. t2 10 ns min CS pulse width low. t3 10 ns min WR pulse width low. t4 0 ns min CS to WR falling edge setup time. t5 0 ns min WR to CS rising edge hold time. t6 4.5 ns min Data to WR rising edge setup time. t7 4.5 ns min Data to WR rising edge hold time. t8 20 ns min WR pulse width high. t9 240 ns min Minimum WR cycle time (single-channel write). t104 0/30 ns min/max WR rising edge to BUSY falling edge. t114 330 ns max BUSY pulse width low (single-channel update). See . Table 10 t12 0 ns min BUSY rising edge to WR rising edge. t13 30 ns min WR rising edge to LDAC falling edge. t14 20 ns min LDAC pulse width low. t154 150 ns typ BUSY rising edge to DAC output response time. t16 20 ns min LDAC rising edge to WR rising edge. t17 0 ns min BUSY rising edge to LDAC falling edge. t18 100 ns typ LDAC falling edge to DAC output response time. t19 20/30 μs typ/ max DAC output settling time. t20 10 ns min CLR pulse width low. t21 350 ns max CLR/RESET pulse activation time. t22 10 ns min RESET pulse width low. t23 120 μs max RESET time indicated by BUSY low. 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with tr = tf = 2 ns (10% to 90% of VCC), and timed from a voltage level of 1.2 V. 3 See Figure 6. 4 Measured with load circuit shown in Figure 2. |
Numéro de pièce similaire - AD5379ABC |
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Description similaire - AD5379ABC |
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