REV. 0

ADE7751

–6–

Pin No.

Mnemonic

Description

13, 14

S1, S0

These logic inputs are used to select one of four possible frequencies for the digital-to-frequency

conversion. This offers the designer greater flexibility when designing the energy meter. See Select-

ing a Frequency for an Energy Meter Application section.

15, 16

G1, G0

These logic inputs are used to select one of four possible gains for the analog inputs V1A and V1B.

The possible gains are 1, 2, 8, and 16. See Analog Inputs section.

17

CLKIN

An external clock can be provided at this logic input. Alternatively, a parallel resonant AT crystal can

be connected across CLKIN and CLKOUT to provide a clock source for the ADE7751. The clock

frequency for specified operation is 3.579545 MHz. Crystal load capacitors of between 22 pF

and 33 pF (ceramic) should be used with the gate oscillator circuit.

18

CLKOUT

A crystal can be connected across this pin and CLKIN as described above to provide a clock source

for the ADE7751. The CLKOUT pin can drive one CMOS load when an external clock is supplied

at CLKIN or by the gate oscillator circuit.

19

FAULT

This logic output will go active high when a fault condition occurs. A fault is defined as a condition

under which the signals on V1A and V1B differ by more than 12.5%. The logic output will be reset

to zero when a fault condition is no longer detected. See Fault Detection section.

20

REVP

This logic output will go logic high when negative power is detected, i.e., when the phase angle

between the voltage and current signals is greater that 90

°. This output is not latched and will be

reset when positive power is once again detected. The output will go high or low at the same time as

a pulse is issued on CF.

21

DGND

This provides the ground reference for the digital circuitry in the ADE7751, i.e., multiplier, filter,

and digital-to-frequency converter. This pin should be tied to the analog ground plane of the PCB.

The digital ground plane is the ground reference for all digital circuitry, e.g., counters (mechanical

and digital), MCUs, and indicator LEDs. For good noise suppression, the analog ground plane

should only be connected to the digital ground plane at one point, e.g., a star ground.

22

CF

Calibration Frequency Logic Output. The CF logic output gives instantaneous real power informa-

tion. This output is intended to be used for calibration purposes. Also see SCF pin description.

23, 24

F2, F1

Low-Frequency Logic Outputs. F1 and F2 supply average real power information. The logic

outputs can be used to directly drive electromechanical counters and 2-phase stepper motors. See

Transfer Function section.

PIN FUNCTION DESCRIPTIONS (continued)

TERMINOLOGY

ADC Offset Error

This refers to the dc offset associated with the analog inputs to

the ADCs. It means that with the analog inputs connected to

AGND the ADCs still see an analog input signal of 1 mV to

10 mV. However, when the HPF is switched on, the offset is

removed from the current channel and the power calculation is

not affected by this offset.

Gain Error

The gain error of the ADE7751 is defined as the difference between

the measured output frequency (minus the offset) and the ideal

output frequency. It is measured with a gain of 1 in Channel

V1A. The difference is expressed as a percentage of the ideal

frequency. The ideal frequency is obtained from the transfer

function—see Transfer Function section.

Gain Error Match

The gain error match is defined as the gain error (minus the

offset) obtained when switching between a gain of 1 and a gain

of 2, 8, or 16. It is expressed as a percentage of the output

frequency obtained under a gain of 1. This gives the gain

error observed when the gain selection is changed from

1 to 2, 8, or 16.

Measurement Error

The error associated with the energy measurement made by the

ADE7751 is defined by the following formula:

Percentage Error =

Energy Registered by the ADE7751 – True Energy

True Energy

× 100%

Phase Error Between Channels

The HPF (high-pass filter) in Channel 1 has a phase lead

response. To offset this phase response and equalize the phase

response between channels, a phase correction network is also

placed in Channel 1. The phase correction network matches the

phase to within

±0.1° over a range of 45 Hz to 65 Hz and ±0.2°

over a range 40 Hz to 1 kHz (see Figures 10 and 11).

Power Supply Rejection

This quantifies the ADE7751 measurement error as a percent-

age of reading when the power supplies are varied.

For the ac PSR measurement, a reading at nominal supplies

(5 V) is taken. A 200 mV rms/100 Hz signal is then introduced

onto the supplies and a second reading is obtained under the

same input signal levels. Any error introduced is expressed as a

percentage of the reading—see Measurement Error definition.

For the dc PSR measurement, a reading at nominal supplies

(5 V) is taken. The supplies are then varied

±5% and a second

reading is obtained with the same input signal levels. Any error

introduced is again expressed as a percentage of the reading.