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TPS40060

TPS40061

www.ti.com

SLUS543F – DECEMBER 2002 – REVISED JUNE 2013

PROGRAMMING CURRENT LIMIT

This device uses a two-tier approach for overcurrent protection. The first tier is a pulse-by-pulse protection

scheme. Current limit is implemented on the high-side MOSFET by sensing the voltage drop across the

MOSFET when the gate is driven low. The MOSFET voltage is compared to the voltage dropped across a

resistor connected from VIN pin to the ILIM pin when driven by a constant current sink. If the voltage drop across

the MOSFET exceeds the voltage drop across the ILIM resistor, the switching pulse is immediately terminated.

The MOSFET remains off until the next switching cycle is initiated.

The second tier consists of a fault counter. The fault counter is incremented on an overcurrent pulse and

decremented on a clock cycle without an overcurrent pulse. When the counter reaches seven (7) a restart is

issued and seven soft-start cycles are initiated. Both the upper and lower MOSFETs are turned off during this

period. The counter is decremented on each soft-start cycle. When the counter is decremented to zero, the PWM

is re-enabled. If the fault has been removed the output starts up normally. If the output is still present the counter

counts seven overcurrent pulses and re-enters the second-tier fault mode. See Figure 7 for typical overcurrent

protection waveforms.

(6)

where:

•

•

•

(7)

BP5, BP10 AND BPN10 INTERNAL VOLTAGE REGULATOR

Start-up characteristics of the BP5, BP10 and BPN10 regulators are shown in Figure 7. Slight variations in the

BP5 occurs dependent upon the switching frequency. Variation in the BPN10 and BP10 regulation characteristics

is also based on the load presented by switching the external MOSFETs.

Copyright © 2002–2013, Texas Instruments Incorporated

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