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L64250JC20 Fiches technique(PDF) 8 Page - InnovASIC, Inc |
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L64250JC20 Fiches technique(HTML) 8 Page - InnovASIC, Inc |
8 / 24 page IA64250 Data Sheet Histogram/Hough Transform Processor August 19, 2008 IA211011114-01 http://www.Innovasic.com Customer Support: Page 8 of 24 1-888-824-4184 I/O Signal Description The diagram below describes the I/O characteristics for each signal on the IC. The signal names correspond to the signal names on the pinout diagrams provide. I/O Characteristics: IODV O When HIGH, ACC RAM or LUT RAM data on the DO bus is valid. VDO.0 - VDO.8 O LUT RAM data output (uses CLK1). CIO.0 - CIO.8 I Control register and LUT input data bus. WE I Used to strobe data into mode latches when LOW. REGADR.0 - REGADR.5 I Selects mode latch, marker or maximum registers. AT I Selects marker and maximum registers when HIGH or mode latches when LOW. AT must be LOW to access the LUT or ACC RAMs via the DO bus. CLK1 I Pixel clock active at rising edge. CLK2 I User I/O clock (may be connected to CLK1) STARTIO I Initiates RAM I/O at HIGH to LOW transition. CX,CY I Used to increment X or Y counters when HIGH. RX,RY I Resets X or Y counters(overrides CX, CY) when HIGH. RESET FP I Resets FP counter when HIGH. PO O Test pin should be left unconnected. |
Numéro de pièce similaire - L64250JC20 |
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Description similaire - L64250JC20 |
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