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ADC101S101 Fiches technique(PDF) 2 Page - Texas Instruments |
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ADC101S101 Fiches technique(HTML) 2 Page - Texas Instruments |
2 / 23 page T/H 12-BIT SUCCESSIVE APPROXIMATION ADC SCLK CS SDATA CONTROL LOGIC VIN ADC121S021 SNAS305H – JULY 2005 – REVISED MARCH 2013 www.ti.com Block Diagram Pin Descriptions Pin No. Name Description ANALOG I/O 3 VIN Analog input. This signal can range from 0V to VA. DIGITAL I/O 4 SCLK Digital clock input. This clock directly controls the conversion and readout processes. 5 SDATA Digital data output. The output samples are clocked out of this pin on falling edges of the SCLK pin. 6 CS Chip select. On the falling edge of CS, a conversion process begins. POWER SUPPLY Positive supply pin. This pin should be connected to a quiet +2.7V to +5.25V source and bypassed to 1 VA GND with a 1 µF capacitor and a 0.1 µF monolithic capacitor located within 1 cm of the power pin. 2 GND The ground return for the supply and signals. For package suffix CISD(X) only, it is recommended that the center pad should be connected to PAD GND ground. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: ADC121S021 |
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