AD7740

REV. A

–7–

GENERAL DESCRIPTION

The AD7740 is a CMOS synchronous Voltage-to-Frequency

Converter (VFC) which uses a charge-balance conversion

technique. The input voltage signal is applied to a proprietary

front-end based around an analog modulator which converts the

input voltage into an output pulse train.

The part also contains an on-chip 2.5 V bandgap reference and

operates from a single 3.3 V or 5 V supply. A block diagram of

the AD7740 is shown in Figure 3.

VIN

INTEGRATOR

FOUT

COMPARATOR

BUF

GND

SWITCHED

CAPS

SWITCHED

CAPS

AD7740

Figure 3. Block Diagram

Input Amplifier Buffering and Voltage Range

The analog input VIN can be buffered by setting BUF = 1. This

presents a high impedance, typically 100 M

Ω, which allows

significant external source impedances to be tolerated. The VIN

voltage range is now 0.1 V to VDD – 0.2 V. By setting BUF = 0

the AD7740 input circuit accepts an analog input below GND

and the analog input VIN has a voltage range from –0.15 V to

VDD + 0.15 V. In this case the input impedance is typically

650 k

Ω.

The transfer function for the AD7740 is represented by:

It is shown in Figure 4 for unbuffered mode.

OUTPUT

FREQUENCY

FOUT

FOUT MIN

INPUT

VOLTAGE

VIN

FOUT MAX

0

–0.15V

AD7740

Figure 4. Transfer Function

Sample Calculation:

VFC Modulator

The analog input signal to the AD7740 is continuously sampled

by a switched capacitor modulator whose sampling rate is set

by a master clock. The input signal may be buffered on-chip

(BUF = 1) before being applied to the sampling capacitor of the

modulator. This isolates the sampling capacitor charging currents

from the analog input pin.

This system is a negative feedback loop that acts to keep the net

charge on the integrator capacitor at zero, by balancing charge

output of the comparator provides the digital input for the 1-bit

DAC, so that the system functions as a negative feedback loop

that acts to minimize the difference signal. See Figure 5.

INTEGRATOR

COMPARATOR

1-BIT

BITSTREAM

INPUT

CLK

AD7740

Figure 5. Modulator Loop

The digital data that represents the analog input voltage is con-

tained in the duty cycle of the pulse train appearing at the output

of the comparator. The output is a pulse train whose frequency

depends on the analog input signal. A full-scale input gives an

facing to either standard logic families or opto-couplers. The

pulsewidth of FOUT is fixed and is determined by the high period

of CLKIN. The pulse is synchronized to the rising edge of the

clock signal. The delay time between the edge of CLKIN and the

edge of FOUT is typically

35 ns. Figure 6 shows the waveform

of this frequency output. (See TPC 8.)

3

3/10

3/10 BUT THE ACTUAL PULSE STREAM VARIES

Figure 6. Frequency Output Waveforms

If there is a step change in input voltage, there is a settling time

that must elapse before valid data is obtained. This is typically

two CLKIN cycles.