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ADV7612WBSWZ Fiches technique(PDF) 5 Page - Analog Devices |
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ADV7612WBSWZ Fiches technique(HTML) 5 Page - Analog Devices |
5 / 20 page Data Sheet ADV7612 Rev. D | Page 5 of 20 DATA AND I2C TIMING CHARACTERISTICS Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit CLOCK AND CRYSTAL Crystal Frequency, XTALP 28.63636 MHz Crystal Frequency Stability ±50 ppm LLC Frequency Range 13.5 170 MHz I2C PORTS SCL Frequency 400 kHz SCL Minimum Pulse Width High1 t1 600 ns SCL Minimum Pulse Width Low1 t2 1.3 µs Start Condition Hold Time1 t3 600 ns Start Condition Setup Time1 t4 600 ns SDA Setup Time1 t5 100 ns SCL and SDA Rise Time1 t6 300 ns SCL and SDA Fall Time1 t7 300 ns Stop Condition Setup Time1 t8 0.6 µs RESET FEATURE Reset Pulse Width 5 ms CLOCK OUTPUTS LLC Mark-Space Ratio1 t9:t10 45:55 55:45 % duty cycle DATA AND CONTROL OUTPUTS2 Data Output Transition Time1 t11 End of valid data to negative clock edge 1.0 2.2 ns t12 Negative clock edge to start of valid data 0.0 0.3 ns I2S PORT, MASTER MODE SCLK Mark-Space Ratio1 t15:t16 45:55 55:45 % duty cycle LRCLK Data Transition Time1 t17 End of valid data to negative SCLK edge 10 ns t18 Negative SCLK edge to start of valid data 10 ns I2S Data Transition Time1 t19 End of valid data to negative SCLK edge 5 ns t20 Negative SCLK edge to start of valid data 5 ns 1 Data guaranteed by characterization. 2 With the DLL block on output clock bypassed. |
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